/**
* This function sets up the device to be a slave.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param SlaveAddr is the address of the slave we are receiving from.
*
* @return None.
*
* @note
* Interrupt is always enabled no matter the tranfer is interrupt-
* driven or polled mode. Whether device will be interrupted or not
* depends on whether the device is connected to an interrupt
* controller and interrupt for the device is enabled.
*
****************************************************************************/
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
{
u32 ControlReg;
u32 BaseAddr;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress;
ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
/*
* Set up master, AckEn, nea and also clear fifo.
*/
ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
ControlReg |= (u32)XIICPS_CR_NEA_MASK;
ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr);
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
return;
}
/*
* IIC Init
*/
int iic_init(XIicPs *IicPs, u16 DeviceId, u32 ClkRate) {
int Status;
XIicPs_Config *IicPs_Config;
XIicPs_DisableAllInterrupts(IicPs->Config.BaseAddress);
/*
* Initialize the IIC driver.
*/
IicPs_Config = XIicPs_LookupConfig(DeviceId);
if (IicPs_Config == NULL) {
myprintf("No XIicPs instance found for ID %d\n\r", DeviceId);
return XST_FAILURE;
}
Status = XIicPs_CfgInitialize(IicPs, IicPs_Config,
IicPs_Config->BaseAddress);
if (Status != XST_SUCCESS) {
myprintf("XIicPs Initialization failed for ID %d\n\r", DeviceId);
return XST_FAILURE;
}
/*
* Set the IIC serial clock rate.
*/
//Status = XIicPs_SetSClk(IicPs, ClkRate);
Status = SetIiCSClk(IicPs, ClkRate);
if (Status != XST_SUCCESS) {
myprintf("Setting XIicPs clock rate failed for ID %d, Status: %d\n\r",
DeviceId, Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* This function prepares a device to transfers as a master.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @param Role specifies whether the device is sending or receiving.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if bus is busy.
*
* @note Interrupts are always disabled, device which needs to use
* interrupts needs to setup interrupts after this call.
*
****************************************************************************/
static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
{
u32 ControlReg;
u32 BaseAddr;
u32 EnabledIntr = 0x0;
Xil_AssertNonvoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
/*
* Only check if bus is busy when repeated start option is not set.
*/
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
if (XIicPs_BusIsBusy(InstancePtr)) {
return XST_FAILURE;
}
}
/*
* Set up master, AckEn, nea and also clear fifo.
*/
ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK |
XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK;
if (Role == RECVING_ROLE) {
ControlReg |= XIICPS_CR_RD_WR_MASK;
EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK;
}else {
ControlReg &= ~XIICPS_CR_RD_WR_MASK;
}
EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr);
return XST_SUCCESS;
}
/*
* This function prepares a device to transfers as a master.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @param Role specifies whether the device is sending or receiving.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if bus is busy.
*
* @note Interrupts are always disabled, device which needs to use
* interrupts needs to setup interrupts after this call.
*
****************************************************************************/
static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
{
u32 ControlReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
/*
* Only check if bus is busy when repeated start option is not set.
*/
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
return (s32)XST_FAILURE;
}
}
/*
* Set up master, AckEn, nea and also clear fifo.
*/
ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
if (Role == RECVING_ROLE) {
ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
}else {
ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
}
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr);
return (s32)XST_SUCCESS;
}