XStatus
init_ll_fifo(struct xemac_s *xemac)
{
xlltemacif_s *xlltemacif = (xlltemacif_s *)(xemac->state);
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xlltemacif->llfifo,
XLlTemac_LlDevBaseAddress(&xlltemacif->lltemac));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
#if NO_SYS
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xlltemacif->lltemac.Config.LLFifoIntr)
| (1 << xlltemacif->lltemac.Config.TemacIntr);
/* set new mask */
XIntc_mEnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
enable_interrupt(xlltemacif->lltemac.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xlltemacif->lltemac.Config.LLFifoIntr);
#endif
return 0;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
#ifdef OS_IS_FREERTOS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr,
AXIETH_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
AXIFIFO_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
#ifdef OS_IS_XILKERNEL
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#endif
#endif
#endif
return 0;
}
/**
*
* This function demonstrates the usage of AXI FIFO
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the Axi FIFO Device.
* - Set up the interrupt handler for fifo
* - Transmit the data
* - Compare the data
* - Return the result
*
* @param InstancePtr is a pointer to the instance of the
* XLlFifo instance.
* @param DeviceId is Device ID of the Axi Fifo Deive instance,
* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId)
{
XLlFifo_Config *Config;
int Status;
int i;
int err;
Status = XST_SUCCESS;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Reset value */
Status = XLlFifo_Status(InstancePtr);
XLlFifo_IntClear(InstancePtr,0xffffffff);
Status = XLlFifo_Status(InstancePtr);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(InstancePtr));
return XST_FAILURE;
}
/*
* Connect the Axi Streaming FIFO to the interrupt subsystem such
* that interrupts can occur. This function is application specific.
*/
Status = SetupInterruptSystem(&Intc, InstancePtr, FIFO_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
XLlFifo_IntEnable(InstancePtr, XLLF_INT_ALL_MASK);
Done = 0;
/* Transmit the Data Stream */
Status = TxSend(InstancePtr, SourceBuffer);
if (Status != XST_SUCCESS){
xil_printf("Transmission of Data failed\n\r");
return XST_FAILURE;
}
while(!Done);
/* Check for errors */
if(Error) {
xil_printf("Errors in the FIFO\n\r");
return XST_FAILURE;
}
err = 0;
/* Compare the data sent with the data received */
xil_printf("Comparing data...\n\r");
for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
err = 1;
break;
}
}
if (err != 0){
return XST_FAILURE;
}
DisableIntrSystem(&Intc, FIFO_INTR_ID);
return Status;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#endif
return 0;
}
