static
void hw_op_matrix_alg_pre_op(const Hw_Op *self)
{
// Flush data cache for data source buffers
Xil_DCacheFlushRange(self->args[0], MATRIX_WIDTH * MATRIX_WIDTH * sizeof(data_t));
Xil_DCacheFlushRange(self->args[1], MATRIX_WIDTH * MATRIX_WIDTH * sizeof(data_t));
}
/**
*
* This function sets up the DMA engine to be ready for scatter gather transfer
*
* @param InstancePtr is pointer to the XAxiCdma instance.
*
* @return
* - XST_SUCCESS if the setup is successful
* - XST_FAILURE if error occurs
*
* @note None
*
******************************************************************************/
static int SetupTransfer(XAxiCdma * InstancePtr)
{
int Status;
XAxiCdma_Bd BdTemplate;
int BdCount;
u8 *SrcBufferPtr;
int Index;
/* Disable all interrupts
*/
XAxiCdma_IntrDisable(InstancePtr, XAXICDMA_XR_IRQ_ALL_MASK);
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
Status = XAxiCdma_BdRingCreate(InstancePtr, BD_SPACE_BASE,
BD_SPACE_BASE, XAXICDMA_BD_MINIMUM_ALIGNMENT, BdCount);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Create BD ring failed %d\r\n",
Status);
return XST_FAILURE;
}
/*
* Setup a BD template to copy to every BD.
*/
XAxiCdma_BdClear(&BdTemplate);
Status = XAxiCdma_BdRingClone(InstancePtr, &BdTemplate);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Clone BD ring failed %d\r\n",
Status);
return XST_FAILURE;
}
/* Initialize receive buffer to 0's and transmit buffer with pattern
*/
memset((void *)ReceiveBufferPtr, 0,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
SrcBufferPtr = (u8 *)TransmitBufferPtr;
for(Index = 0; Index < MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER; Index++) {
SrcBufferPtr[Index] = Index & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((UINTPTR)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)ReceiveBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#endif
return XST_SUCCESS;
}
void metal_machine_cache_flush(void *addr, unsigned int len)
{
if (!addr & !len)
Xil_DCacheFlush();
else
Xil_DCacheFlushRange((intptr_t)addr, len);
}
/**
*
* API to setup ADMA2 descriptor table
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param BlkCnt - block count.
* @param Buff pointer to data buffer.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
{
u32 TotalDescLines = 0;
u32 DescNum = 0;
u32 BlkSize = 0;
/*
* Setup ADMA2 - Write descriptor table and point ADMA SAR to it
*/
BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_BLK_SIZE_OFFSET);
BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
TotalDescLines = 1;
}else {
TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
if ((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH)
TotalDescLines += 1;
}
for (DescNum = 0; DescNum < (TotalDescLines-1); DescNum++) {
InstancePtr->Adma2_DescrTbl[DescNum].Address =
(u32)(Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
/*
* This will write '0' to length field which indicates 65536
*/
InstancePtr->Adma2_DescrTbl[DescNum].Length =
(u16)XSDPS_DESC_MAX_LENGTH;
}
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
(u32)(Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
(BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH);
XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
(u32)&(InstancePtr->Adma2_DescrTbl[0]));
Xil_DCacheFlushRange(&(InstancePtr->Adma2_DescrTbl[0]),
sizeof(XSdPs_Adma2Descriptor) * 32);
}
/**
* Perform DCache range related API test such as Xil_DCacheFlushRange and
* Xil_DCacheInvalidateRange. This test function writes a constant value
* to the Data array, flushes the range, writes a new value, then invalidates
* the corresponding range.
*
* @return
*
* - 0 is returned for a pass
* - -1 is returned for a failure
*/
int Xil_TestDCacheRange(void)
{
int Index;
int Status;
u32 Value;
print("-- Cache Range Test --\n\r");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0xA0A00505;
print(" initialize Data done:\r\n");
Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32));
print(" flush range done\r\n");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = Index + 3;
Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32));
print(" invalidate dcache range done\r\n");
Status = 0;
for (Index = 0; Index < DATA_LENGTH; Index++) {
Value = Data[Index];
if (Value != 0xA0A00505) {
Status = -1;
xil_printf("Data[%d] = %x\r\n", Index, Value);
break;
}
}
if (!Status) {
print(" Invalidate worked\r\n");
}
else {
print("Error: Invalidate dcache range not working\r\n");
}
print("-- Cache Range Test Complete --\r\n");
return Status;
}
/***************************************************************************//**
* @brief dac_write_custom_data
*******************************************************************************/
void dac_write_custom_data(dac_core *core,
const uint32_t *custom_data_iq,
uint32_t custom_tx_count)
{
uint32_t index;
uint32_t index_mem = 0;
uint32_t length;
uint32_t dmac_flags;
uint8_t chan;
uint8_t num_tx_channels = core->no_of_channels / 2;
for(index = 0; index < custom_tx_count; index++)
{
for (chan = 0; chan < num_tx_channels; chan++) // send the same data on all the channels
{
Xil_Out32(core->dac_ddr_baseaddr + index_mem * sizeof(uint32_t), custom_data_iq[index]);
index_mem++;
}
}
Xil_DCacheFlushRange(core->dac_ddr_baseaddr, index_mem * sizeof(uint32_t));
length = index_mem * 4;
switch (core->dma_type)
{
case DMA_STREAM:
dmac_flags = 0;
break;
case DMA_CYCLIC:
dmac_flags = AXI_DMAC_FLAG_CYCLIC;
break;
case DMA_PLDDR_FIFO:
dmac_flags = AXI_DMAC_FLAG_LAST;
break;
}
dac_dma_write(AXI_DMAC_REG_CTRL, 0);
dac_dma_write(AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
dac_dma_write(AXI_DMAC_REG_FLAGS, dmac_flags);
dac_dma_write(AXI_DMAC_REG_SRC_ADDRESS, core->dac_ddr_baseaddr);
dac_dma_write(AXI_DMAC_REG_SRC_STRIDE, 0x0);
dac_dma_write(AXI_DMAC_REG_X_LENGTH, length - 1);
dac_dma_write(AXI_DMAC_REG_Y_LENGTH, 0x0);
dac_dma_write(AXI_DMAC_REG_START_TRANSFER, 0x1);
}
// --------------------------------------------------------
volatile void* vbx_uncached_malloc(size_t size)
{
void *p;
#if VBX_DEBUG_MALLOC
printf("uncached_malloc %d bytes\n", size);
#endif
p = malloc(size);
if (!p) {
#if VBX_DEBUG_MALLOC
VBX_PRINTF("ERROR: uncached_malloc failed.\n");
VBX_FATAL(__LINE__, __FILE__, -1);
#endif
return NULL;
}
Xil_DCacheFlushRange((u32) p, size);
return (volatile void *) VBX_UNCACHED_ADDR(p);
}
void DisplayDemoInvertFrame(u32 *srcFrame, u32 *destFrame, u32 width, u32 height, u32 stride)
{
u32 xcoi, ycoi;
u32 lineStart = 0;
for(ycoi = 0; ycoi < height; ycoi++)
{
for(xcoi = 0; xcoi < width; xcoi++)
{
destFrame[xcoi + lineStart] = ~srcFrame[xcoi + lineStart];
}
lineStart += stride / 4; /*The stride is in bytes, so it needs to be divided by four to get the u32 address*/
}
/*
* Flush the framebuffer memory range to ensure changes are written to the
* actual memory, and therefore accessible by the VDMA.
*/
Xil_DCacheFlushRange((unsigned int) destFrame, DISPLAYDEMO_MAX_FRAME * 4);
}
void DemoInvertFrame(u8 *srcFrame, u8 *destFrame, u32 width, u32 height, u32 stride)
{
u32 xcoi, ycoi;
u32 lineStart = 0;
for(ycoi = 0; ycoi < height; ycoi++)
{
for(xcoi = 0; xcoi < (width * 3); xcoi+=3)
{
destFrame[xcoi + lineStart] = ~srcFrame[xcoi + lineStart]; //Red
destFrame[xcoi + lineStart + 1] = ~srcFrame[xcoi + lineStart + 1]; //Blue
destFrame[xcoi + lineStart + 2] = ~srcFrame[xcoi + lineStart + 2]; //Green
}
lineStart += stride;
}
/*
* Flush the framebuffer memory range to ensure changes are written to the
* actual memory, and therefore accessible by the VDMA.
*/
Xil_DCacheFlushRange((unsigned int) destFrame, DEMO_MAX_FRAME);
}
/**
* Inject errors using the hardware fault injection functionality, and write
* random data and read it back using the indicated location.
*
* @param InstancePtr is a pointer to the XBram instance to
* be worked on.
* @param The Addr is the indicated memory location to use
* @param The Index1 is the bit location of the first injected error
* @param The Index2 is the bit location of the second injected error
* @param The Width is the data byte width
* @param The ActualData is filled in with expected data for checking
* @param The ActualEcc is filled in with expected ECC for checking
*
* @return None
*
* @note None.
*
******************************************************************************/
static void InjectErrors(XBram * InstancePtr, u32 Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc)
{
u32 InjectedData = 0;
u32 InjectedEcc = 0;
u32 RandomData = PrngData(&PrngResult);
if (Index1 < 32) {
InjectedData = 1 << Index1;
} else {
InjectedEcc = 1 << (Index1 - 32);
}
if (Index2 < 32) {
InjectedData |= (1 << Index2);
} else {
InjectedEcc |= 1 << (Index2 - 32);
}
WR(FI_D_0_OFFSET, InjectedData);
WR(FI_ECC_0_OFFSET, InjectedEcc);
XBram_Out32(Addr, RandomData);
Xil_DCacheFlushRange(Addr, 4);
switch (Width) {
case 1: /* Byte - Write to do Read-Modify-Write */
XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
break;
case 2: /* Halfword - Write to do Read-Modify-Write */
XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
break;
case 4: /* Word - Read */
(void) XBram_In32(Addr);
break;
}
*ActualData = InjectedData ^ RandomData;
*ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
}
/****************************************************************************
*
* Invalidate the entire Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidate(void)
{
u32 currmask;
u32 stack_start,stack_end,stack_size;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
stack_end = (u32 )&_stack_end;
stack_start = (u32 )&__undef_stack;
stack_size = stack_start-stack_end;
/* Flush stack memory to save return address */
Xil_DCacheFlushRange(stack_end, stack_size);
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
/*invalidate all D cache*/
mtcp(XREG_CP15_INVAL_DC_ALL, 0);
mtcpsr(currmask);
}
/*
*
* This function non-blockingly transmits all packets through the DMA engine.
*
* @param AxiDmaInstPtr points to the DMA engine instance
*
* @return
* - XST_SUCCESS if the DMA accepts all the packets successfully,
* - XST_FAILURE if error occurs
*
* @note None.
*
******************************************************************************/
static int SendPacket(XAxiDma * AxiDmaInstPtr, u8 TDest, u8 TId, u8 Value)
{
XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
u8 *TxPacket;
XAxiDma_Bd *BdPtr, *BdCurPtr;
int Status;
int Index, Pkts;
u32 BufferAddr;
/*
* Each packet is limited to TxRingPtr->MaxTransferLen
*
* This will not be the case if hardware has store and forward built in
*/
if (MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT > TxRingPtr->MaxTransferLen) {
xil_printf("Invalid total per packet transfer length for the "
"packet %d/%d\r\n",
MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT,
TxRingPtr->MaxTransferLen);
return XST_INVALID_PARAM;
}
TxPacket = (u8 *) Packet;
for(Index = 0; Index < MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER;
Index ++) {
TxPacket[Index] = Value;
Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN *
NUMBER_OF_BDS_TO_TRANSFER);
Status = XAxiDma_BdRingAlloc(TxRingPtr,
NUMBER_OF_BDS_TO_TRANSFER,
&BdPtr);
if (Status != XST_SUCCESS) {
xil_printf("Failed bd alloc\r\n");
return XST_FAILURE;
}
BufferAddr = (u32) TxPacket;
BdCurPtr = BdPtr;
/*
* Set up the BD using the information of the packet to transmit
* Each transfer has NUMBER_OF_BDS_PER_PKT BDs
*/
for(Index = 0; Index < NUMBER_OF_PKTS_TO_TRANSFER; Index++) {
for(Pkts = 0; Pkts < NUMBER_OF_BDS_PER_PKT; Pkts++) {
u32 CrBits = 0;
Status = XAxiDma_BdSetBufAddr(BdCurPtr, BufferAddr);
if (Status != XST_SUCCESS) {
xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
(unsigned int)BufferAddr,
(unsigned int)BdCurPtr, Status);
return XST_FAILURE;
}
Status = XAxiDma_BdSetLength(BdCurPtr, HSIZE,
TxRingPtr->MaxTransferLen);
if (Status != XST_SUCCESS) {
xil_printf("Tx set length %d on BD %x failed %d\r\n",
MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
return XST_FAILURE;
}
if (Pkts == 0) {
/* The first BD has SOF set
*/
CrBits |= XAXIDMA_BD_CTRL_TXSOF_MASK;
#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
/* The first BD has total transfer length set
* in the last APP word, this is for the
* loopback widget
*/
Status = XAxiDma_BdSetAppWord(BdCurPtr,
XAXIDMA_LAST_APPWORD,
MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT);
if (Status != XST_SUCCESS) {
xil_printf("Set app word failed with %d\r\n",
Status);
}
#endif
}
if(Pkts == (NUMBER_OF_BDS_PER_PKT - 1)) {
/* The last BD should have EOF and IOC set
*/
CrBits |= XAXIDMA_BD_CTRL_TXEOF_MASK;
}
XAxiDma_BdSetCtrl(BdCurPtr, CrBits);
XAxiDma_BdSetId(BdCurPtr, BufferAddr);
XAxiDma_BdSetTId(BdCurPtr, TId);
XAxiDma_BdSetTDest(BdCurPtr, TDest);
XAxiDma_BdSetTUser(BdCurPtr, TUSER);
XAxiDma_BdSetARCache(BdCurPtr, ARCACHE);
XAxiDma_BdSetARUser(BdCurPtr, ARUSER);
XAxiDma_BdSetVSize(BdCurPtr, VSIZE);
XAxiDma_BdSetStride(BdCurPtr, STRIDE);
BufferAddr += MAX_PKT_LEN;
BdCurPtr = XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
}
}
/* Give the BD to hardware */
Status = XAxiDma_BdRingToHw(TxRingPtr, NUMBER_OF_BDS_TO_TRANSFER,
BdPtr);
if (Status != XST_SUCCESS) {
xil_printf("Failed to hw, length %d\r\n",
(int)XAxiDma_BdGetLength(BdPtr,
TxRingPtr->MaxTransferLen));
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
* This function sends a given data buffer.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
* @param EpNum is the number of the endpoint to receive data from.
* @param BufferPtr is a pointer to the buffer to send.
* @param BufferLen is the Buffer length.
*
* @return
* - XST_SUCCESS: The operation completed successfully.
* - XST_FAILURE: An error occured.
* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
*
******************************************************************************/
int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
const u8 *BufferPtr, u32 BufferLen)
{
int Status;
u32 Token;
XUsbPs_EpIn *Ep;
XUsbPs_dTD *DescPtr;
u32 Length;
u32 PipeEmpty = 1;
u32 Mask = 0x00010000;
u32 BitMask = Mask << EpNum;
u32 RegValue;
u32 Temp;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
/* Locate the next available buffer in the ring. A buffer is available
* if its descriptor is not active.
*/
Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
if(Ep->dTDTail != Ep->dTDHead) {
PipeEmpty = 0;
}
XUsbPs_dTDInvalidateCache(Ep->dTDHead);
/* Tell the caller if we do not have any descriptors available. */
if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
return XST_USB_NO_DESC_AVAILABLE;
}
/* Remember the current head. */
DescPtr = Ep->dTDHead;
do {
Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
/* Attach the provided buffer to the current descriptor.*/
Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
BufferLen -= Length;
BufferPtr += Length;
XUsbPs_dTDSetActive(Ep->dTDHead);
if(BufferLen == 0)
XUsbPs_dTDSetIOC(Ep->dTDHead);
XUsbPs_dTDClrTerminate(Ep->dTDHead);
XUsbPs_dTDFlushCache(Ep->dTDHead);
/* Advance the head descriptor pointer to the next descriptor. */
Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
/* Terminate the next descriptor and flush the cache.*/
XUsbPs_dTDInvalidateCache(Ep->dTDHead);
/* Tell the caller if we do not have any descriptors available. */
if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
return XST_USB_NO_DESC_AVAILABLE;
}
} while(BufferLen);
XUsbPs_dTDSetTerminate(Ep->dTDHead);
XUsbPs_dTDFlushCache(Ep->dTDHead);
if(!PipeEmpty) {
/* Read the endpoint prime register. */
RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
if(RegValue & BitMask) {
return XST_SUCCESS;
}
do {
RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
RegValue | XUSBPS_CMD_ATDTW_MASK);
Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
& BitMask;
} while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
XUSBPS_CMD_ATDTW_MASK));
RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
RegValue & ~XUSBPS_CMD_ATDTW_MASK);
if(Temp) {
return XST_SUCCESS;
}
}
/* Check, if the DMA engine is still running. If it is running, we do
* not clear Queue Head fields.
*
* Same cache rule as for the Transfer Descriptor applies for the Queue
* Head.
*/
XUsbPs_dQHInvalidateCache(Ep->dQH);
/* Add the dTD to the dQH */
XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
XUsbPs_dQHFlushCache(Ep->dQH);
Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
return Status;
}
/**
*
* API to set high speed in card and host. Changes clock in host accordingly.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
int XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
{
u32 Status = 0;
u32 StatusReg = 0x0;
u32 Arg = 0;
#if( ffconfigSDIO_DRIVER_USES_INTERRUPT == 0 )
u32 ulPollCount;
#endif
#ifndef MMC_CARD
/* u32 ClockReg; */
#ifdef __ICCARM__
#pragma data_alignment = 32
u8 ReadBuff[64];
#pragma data_alignment = 4
#else
u8 ReadBuff[64] __attribute__ ((aligned(32)));
#endif
u16 BlkCnt;
u16 BlkSize;
#endif
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifndef MMC_CARD
BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
BlkSize &= XSDPS_BLK_SIZE_MASK;
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_BLK_SIZE_OFFSET, BlkSize);
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
Xil_DCacheFlushRange( ( unsigned )ReadBuff, 64);
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_XFER_MODE_OFFSET,
XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
Arg = XSDPS_SWITCH_CMD_HS_SET;
Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
#if( ffconfigSDIO_DRIVER_USES_INTERRUPT != 0 )
StatusReg = XSdPs_WaitInterrupt( InstancePtr, XSDPS_INTR_ERR_MASK | XSDPS_INTR_TC_MASK );
if( ( StatusReg & XSDPS_INTR_TC_MASK ) != 0 )
{
Status = XST_SUCCESS;
}
else
{
Status = XST_FAILURE;
goto RETURN_PATH;
}
#else
/*
* Check for transfer complete
* Polling for response
* Limit the time spent here with a simpler counter 'ulPollCount'
*/
ulPollCount = 0;
do {
StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET);
if (StatusReg & XSDPS_INTR_ERR_MASK) {
/*
* Write to clear error bits
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_ERR_INTR_STS_OFFSET,
XSDPS_ERROR_INTR_ALL_MASK);
Status = XST_FAILURE;
goto RETURN_PATH;
}
ulPollCount++;
if( ulPollCount == POLLCOUNT_MAX )
{
Status = XST_FAILURE;
goto RETURN_PATH;
}
} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
/*
* Write to clear bit
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
#endif /* ffconfigSDIO_DRIVER_USES_INTERRUPT */
/*
* Change the clock frequency to 50 MHz
*/
Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET);
StatusReg |= XSDPS_HC_SPEED_MASK;
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET,StatusReg);
Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_RESP0_OFFSET);
#else
Arg = XSDPS_MMC_HIGH_SPEED_ARG;
Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
#ifdef __arm__
usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
#endif
#ifdef __MICROBLAZE__
/* 2 msec delay */
MB_Sleep(2);
#endif
XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET);
StatusReg |= XSDPS_HC_SPEED_MASK;
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET,StatusReg);
Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_RESP0_OFFSET);
#endif
Status = XST_SUCCESS;
RETURN_PATH:
return Status;
}
/**
* Sets bits contained in multiple LUTs specified by the coordinates and data in the lut_configs array.
*
* @return XST_SUCCESS or XST_FAILURE.
**/
int MiCAP_Custom_SetMultiClbBits(XGpio* gpio_InstancePtr, XAxiDma* dma_InstancePtr,LUT_config_type *lut_configs, u32 num_lut_configs) {
u8 bottom_ntop;
int Status;
int clock_row;
u32 major_frame_address;
u32 word_offset;
assert(num_lut_configs>0);
long slice_row = lut_configs[0].slice_row;
long slice_col = lut_configs[0].slice_col;
// Check if all the lutconfigs are indeed part of the same set of frames
u32 i;
for(i = 1; i<num_lut_configs; i++) {
if(!MiCAP_Custom_IsSameFrame(slice_row, slice_col, lut_configs[i].slice_row, lut_configs[i].slice_col))
return XST_FAILURE;
}
MiCAP_GetConfigurationCoordinates(slice_row, slice_col,
&bottom_ntop, &clock_row, &major_frame_address, &word_offset);
u32 frame_num = 4;
u32 frame_number_offset;
if(lut_configs[0].Resource[0][1] < 32)
frame_number_offset = 26;
else
frame_number_offset = 32;
u32 buffer[506];
u32 frame_address = XHwIcap_Custom_SetupFar7series(bottom_ntop, XHI_FAR_CLB_BLOCK, clock_row, major_frame_address, frame_number_offset);
u32 Read_frame_TxBuffer[] = {0xFFFFFFFF, 0xFFFFFFFF,0xAA995566, 0x20000000, 0x20000000, 0x30008001, 0x00000007,
0x20000000, 0x20000000, 0x30008001, 0x00000004, 0x20000000, 0x20000000,
0x20000000, 0x30002001, frame_address, 0x28006000, 0x480001FA, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x30008001, 0x0000000D, 0x20000000, 0x20000000,0xFFFFFFFF,
0xFFFFFFFF,0xFFFFFFFF};
memcpy(TxBufferPtr_rdFrame, Read_frame_TxBuffer, 57 * sizeof(u32));
// Frame Read:
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
Xil_DCacheFlushRange((u32)TxBufferPtr_rdFrame, MAX_PKT_LEN_rdFrame);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x4); // assert read ctrl
//gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
while(!(gpio_stat & 0x4)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x5); // assert read ctrl + reset release
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) TxBufferPtr_rdFrame,
57*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DMA_TO_DEVICE)) {
}
while(!(gpio_stat & 0x1)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
//2) Reading the frames back
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) RxBufferPtr_rdFrame,
MAX_PKT_LEN_rdFrame, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x10);
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DEVICE_TO_DMA)) {
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0); // Put data source back in reset state for next run
Xil_DCacheFlushRange((u32)RxBufferPtr_rdFrame, 540*4);
u32 *configuration = buffer + 101 + 1 + 1;
for(i = 0; i< num_lut_configs; i++) {
u32 word_offset = MiCAP_Custom_GetWordOffset(lut_configs[i].slice_row);
MiCAP_Custom_SetClbBitsInConfig(configuration, word_offset,
frame_num, frame_number_offset, lut_configs[i].Resource, lut_configs[i].Value, lut_configs[i].NumBits);
}
//3: Frame Write
u32 head[] = {0xFFFFFFFF, 0xFFFFFFFF, 0x20000000, 0xAA995566, 0x20000000, 0x20000000,
0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30018001, 0x03727093,
0x30002001, frame_address, 0x30008001, 0x00000001, 0x20000000, 0x300041F9};
u32 tail[] = {0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30002001, 0x00061080,
0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30008001, 0x0000000D,
0x20000000, 0x20000000,0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
for (j=0; j<18; j++){
TxBufferPtr_wrFrame[j] = head[j];
}
for (i=0; i<505; i++){
TxBufferPtr_wrFrame[j] = configuration[i];
j++;
}
for (i=0; i<17;i++){
TxBufferPtr_wrFrame[j] = tail[i];
j++;
}
Xil_DCacheFlushRange((u32)TxBufferPtr_wrFrame, 540*4);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
//Xil_DCacheFlushRange((u32)TxBufferPtr_rdFrame, MAX_PKT_LEN_rdFrame);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x2); // assert write ctrl
//gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
while(!(gpio_stat & 0x4)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x3); // assert write ctrl + reset release
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) TxBufferPtr_wrFrame,
540*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DMA_TO_DEVICE)) {
}
while(!(gpio_stat & 0x2)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x10);
return XST_SUCCESS;
}
/*
* This function setup the driver for scatter gather transfer
*
* @param InstancePtr is a pointer to the XAxiCdma instance
*
* @return
* - XST_SUCCESS if setup successful
* - XST_FAILURE if setup failed with error
*
* @note None.
*
******************************************************************************/
static int SetupSgTransfer(XAxiCdma *InstancePtr)
{
int Status;
XAxiCdma_Bd BdTemplate;
int BdCount;
u8 *SrcBufferPtr;
int Index;
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
Status = XAxiCdma_BdRingCreate(InstancePtr, BD_SPACE_BASE,
BD_SPACE_BASE, XAXICDMA_BD_MINIMUM_ALIGNMENT, BdCount);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Create BD ring failed %d\r\n",
Status);
return XST_FAILURE;
}
/*
* Setup a BD template to copy to every BD.
*/
XAxiCdma_BdClear(&BdTemplate);
Status = XAxiCdma_BdRingClone(InstancePtr, &BdTemplate);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Clone BD ring failed %d\r\n",
Status);
return XST_FAILURE;
}
/* Initialize receive buffer to 0's and transmit buffer with pattern
*/
memset((void *)ReceiveBufferPtr, 0,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
SrcBufferPtr = (u8 *)TransmitBufferPtr;
for(Index = 0; Index < MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER;
Index++) {
SrcBufferPtr[Index] = Index & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
/* Setup interrupt coalescing and delay timer
*/
Status = XAxiCdma_SetCoalesce(InstancePtr, COALESCING_COUNT,
DELAY_COUNT);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Set coalescing failed %d\r\n", Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* This function transmits one packet non-blockingly through the DMA engine.
*
* @param AxiDmaInstPtr points to the DMA engine instance
*
* @return - XST_SUCCESS if the DMA accepts the packet successfully,
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
static int SendPacket(XAxiDma * AxiDmaInstPtr)
{
XAxiDma_BdRing *TxRingPtr;
u8 *TxPacket;
u8 Value;
XAxiDma_Bd *BdPtr;
int Status;
int Index;
TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
/* Create pattern in the packet to transmit */
TxPacket = (u8 *) Packet;
Value = TEST_START_VALUE;
for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
TxPacket[Index] = Value;
Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN);
/* Allocate a BD */
Status = XAxiDma_BdRingAlloc(TxRingPtr, 1, &BdPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Set up the BD using the information of the packet to transmit */
Status = XAxiDma_BdSetBufAddr(BdPtr, (u32) Packet);
if (Status != XST_SUCCESS) {
xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
(unsigned int)Packet, (unsigned int)BdPtr, Status);
return XST_FAILURE;
}
Status = XAxiDma_BdSetLength(BdPtr, MAX_PKT_LEN,
TxRingPtr->MaxTransferLen);
if (Status != XST_SUCCESS) {
xil_printf("Tx set length %d on BD %x failed %d\r\n",
MAX_PKT_LEN, (unsigned int)BdPtr, Status);
return XST_FAILURE;
}
#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
Status = XAxiDma_BdSetAppWord(BdPtr,
XAXIDMA_LAST_APPWORD, MAX_PKT_LEN);
/* If Set app length failed, it is not fatal
*/
if (Status != XST_SUCCESS) {
xil_printf("Set app word failed with %d\r\n", Status);
}
#endif
/* For single packet, both SOF and EOF are to be set
*/
XAxiDma_BdSetCtrl(BdPtr, XAXIDMA_BD_CTRL_TXEOF_MASK |
XAXIDMA_BD_CTRL_TXSOF_MASK);
XAxiDma_BdSetId(BdPtr, (u32) Packet);
/* Give the BD to DMA to kick off the transmission. */
Status = XAxiDma_BdRingToHw(TxRingPtr, 1, BdPtr);
if (Status != XST_SUCCESS) {
xil_printf("to hw failed %d\r\n", Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* This function does a minimal DEVICE mode setup on the USB device and driver
* as a design example. The purpose of this function is to illustrate how to
* set up a USB flash disk emulation system.
*
*
* @param IntcInstancePtr is a pointer to the instance of the INTC driver.
* @param UsbInstancePtr is a pointer to the instance of USB driver.
* @param UsbDeviceId is the Device ID of the USB Controller and is the
* XPAR_<USB_instance>_DEVICE_ID value from xparameters.h.
* @param UsbIntrId is the Interrupt Id and is typically
* XPAR_<INTC_instance>_<USB_instance>_IP2INTC_IRPT_INTR value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE on error
*
******************************************************************************/
static int UsbIntrExample(XScuGic *IntcInstancePtr, XUsbPs *UsbInstancePtr,
u16 UsbDeviceId, u16 UsbIntrId)
{
int Status;
u8 *MemPtr = NULL;
int ReturnStatus = XST_FAILURE;
/* For this example we only configure 2 endpoints:
* Endpoint 0 (default control endpoint)
* Endpoint 1 (BULK data endpoint)
*/
const u8 NumEndpoints = 2;
XUsbPs_Config *UsbConfigPtr;
XUsbPs_DeviceConfig DeviceConfig;
/* Initialize the USB driver so that it's ready to use,
* specify the controller ID that is generated in xparameters.h
*/
UsbConfigPtr = XUsbPs_LookupConfig(UsbDeviceId);
if (NULL == UsbConfigPtr) {
goto out;
}
/* We are passing the physical base address as the third argument
* because the physical and virtual base address are the same in our
* example. For systems that support virtual memory, the third
* argument needs to be the virtual base address.
*/
Status = XUsbPs_CfgInitialize(UsbInstancePtr,
UsbConfigPtr,
UsbConfigPtr->BaseAddress);
if (XST_SUCCESS != Status) {
goto out;
}
/* Set up the interrupt subsystem.
*/
Status = UsbSetupIntrSystem(IntcInstancePtr,
UsbInstancePtr,
UsbIntrId);
if (XST_SUCCESS != Status)
{
goto out;
}
/* Configuration of the DEVICE side of the controller happens in
* multiple stages.
*
* 1) The user configures the desired endpoint configuration using the
* XUsbPs_DeviceConfig data structure. This includes the number of
* endpoints, the number of Transfer Descriptors for each endpoint
* (each endpoint can have a different number of Transfer Descriptors)
* and the buffer size for the OUT (receive) endpoints. Each endpoint
* can have different buffer sizes.
*
* 2) Request the required size of DMAable memory from the driver using
* the XUsbPs_DeviceMemRequired() call.
*
* 3) Allocate the DMAable memory and set up the DMAMemVirt and
* DMAMemPhys members in the XUsbPs_DeviceConfig data structure.
*
* 4) Configure the DEVICE side of the controller by calling the
* XUsbPs_ConfigureDevice() function.
*/
/*
* For this example we only configure Endpoint 0 and Endpoint 1.
*
* Bufsize = 0 indicates that there is no buffer allocated for OUT
* (receive) endpoint 0. Endpoint 0 is a control endpoint and we only
* receive control packets on that endpoint. Control packets are 8
* bytes in size and are received into the Queue Head's Setup Buffer.
* Therefore, no additional buffer space is needed.
*/
DeviceConfig.EpCfg[0].Out.Type = XUSBPS_EP_TYPE_CONTROL;
DeviceConfig.EpCfg[0].Out.NumBufs = 2;
DeviceConfig.EpCfg[0].Out.BufSize = 64;
DeviceConfig.EpCfg[0].Out.MaxPacketSize = 64;
DeviceConfig.EpCfg[0].In.Type = XUSBPS_EP_TYPE_CONTROL;
DeviceConfig.EpCfg[0].In.NumBufs = 2;
DeviceConfig.EpCfg[0].In.MaxPacketSize = 64;
DeviceConfig.EpCfg[1].Out.Type = XUSBPS_EP_TYPE_BULK;
DeviceConfig.EpCfg[1].Out.NumBufs = 16;
DeviceConfig.EpCfg[1].Out.BufSize = 512;
DeviceConfig.EpCfg[1].Out.MaxPacketSize = 512;
DeviceConfig.EpCfg[1].In.Type = XUSBPS_EP_TYPE_BULK;
DeviceConfig.EpCfg[1].In.NumBufs = 16;
DeviceConfig.EpCfg[1].In.MaxPacketSize = 512;
DeviceConfig.NumEndpoints = NumEndpoints;
MemPtr = (u8 *)&Buffer[0];
memset(MemPtr,0,MEMORY_SIZE);
Xil_DCacheFlushRange((unsigned int)MemPtr, MEMORY_SIZE);
/* Finish the configuration of the DeviceConfig structure and configure
* the DEVICE side of the controller.
*/
DeviceConfig.DMAMemPhys = (u32) MemPtr;
Status = XUsbPs_ConfigureDevice(UsbInstancePtr, &DeviceConfig);
if (XST_SUCCESS != Status) {
goto out;
}
/* Set the handler for receiving frames. */
Status = XUsbPs_IntrSetHandler(UsbInstancePtr, UsbIntrHandler, NULL,
XUSBPS_IXR_UE_MASK);
if (XST_SUCCESS != Status) {
goto out;
}
/* Set the handler for handling endpoint 0 events. This is where we
* will receive and handle the Setup packet from the host.
*/
Status = XUsbPs_EpSetHandler(UsbInstancePtr, 0,
XUSBPS_EP_DIRECTION_OUT,
XUsbPs_Ep0EventHandler, UsbInstancePtr);
/* Set the handler for handling endpoint 1 events.
*
* Note that for this example we do not need to register a handler for
* TX complete events as we only send data using static data buffers
* that do not need to be free()d or returned to the OS after they have
* been sent.
*/
Status = XUsbPs_EpSetHandler(UsbInstancePtr, 1,
XUSBPS_EP_DIRECTION_OUT,
XUsbPs_Ep1EventHandler, UsbInstancePtr);
/* Enable the interrupts. */
XUsbPs_IntrEnable(UsbInstancePtr, XUSBPS_IXR_UR_MASK |
XUSBPS_IXR_UI_MASK);
/* Start the USB engine */
XUsbPs_Start(UsbInstancePtr);
/* At this point we wait for the user to plug in the usb plug. This
* will cause the host to send USB packets. Once we received something,
* we clean up and stop the controller.
*
* This will not really work if we want to use the USB storage
* example. What can we do instead?
*/
while (NumReceivedFrames < 1) {
/* NOP */
}
/* Set return code to indicate success and fall through to clean-up
* code.
*/
ReturnStatus = XST_SUCCESS;
out:
/* Clean up. It's always safe to disable interrupts and clear the
* handlers, even if they have not been enabled/set. The same is true
* for disabling the interrupt subsystem.
*/
XUsbPs_Stop(UsbInstancePtr);
XUsbPs_IntrDisable(UsbInstancePtr, XUSBPS_IXR_ALL);
(int) XUsbPs_IntrSetHandler(UsbInstancePtr, NULL, NULL, 0);
UsbDisableIntrSystem(IntcInstancePtr, UsbIntrId);
/* Free allocated memory.
*/
if (NULL != UsbInstancePtr->UserDataPtr) {
free(UsbInstancePtr->UserDataPtr);
}
return ReturnStatus;
}
void DisplayDemoPrintTest(u32 *frame, u32 width, u32 height, u32 stride, int pattern)
{
u32 xcoi, ycoi;
u32 iPixelAddr;
u32 wStride;
u32 wRed, wBlue, wGreen, wColor;
u32 wCurrentInt;
double fRed, fBlue, fGreen, fColor;
u32 xLeft, xMid, xRight, xInt;
u32 yMid, yInt;
double xInc, yInc;
switch (pattern)
{
case DISPLAYDEMO_PATTERN_0:
wStride = stride / 4; /* Find the stride in 32-bit words */
xInt = width / 4; //Four intervals, each with width/4 pixels
xLeft = xInt;
xMid = xInt * 2;
xRight = xInt * 3;
xInc = 256.0 / ((double) xInt); //256 color intensities are cycled through per interval (overflow must be caught when color=256.0)
yInt = height / 2; //Two intervals, each with width/2 lines
yMid = yInt;
yInc = 256.0 / ((double) yInt); //256 color intensities are cycled through per interval (overflow must be caught when color=256.0)
fBlue = 0.0;
fRed = 256.0;
for(xcoi = 0; xcoi < width; xcoi++)
{
/*
* Convert color intensities to integers < 256, and trim values >=256
*/
wRed = (fRed >= 256.0) ? 255 : ((u32) fRed);
wBlue = (fBlue >= 256.0) ? 255 : ((u32) fBlue);
wColor = (wRed << BIT_DISPLAY_RED) | (wBlue << BIT_DISPLAY_BLUE);
iPixelAddr = xcoi;
fGreen = 0.0;
for(ycoi = 0; ycoi < height; ycoi++)
{
wGreen = (fGreen >= 256.0) ? 255 : ((u32) fGreen);
frame[iPixelAddr] = wColor | (wGreen << BIT_DISPLAY_GREEN);
if (ycoi < yMid)
{
fGreen += yInc;
}
else
{
fGreen -= yInc;
}
/*
* This pattern is printed one vertical line at a time, so the address must be incremented
* by the stride instead of just 1.
*/
iPixelAddr += wStride;
}
if (xcoi < xLeft)
{
fBlue = 0.0;
fRed -= xInc;
}
else if (xcoi < xMid)
{
fBlue += xInc;
fRed += xInc;
}
else if (xcoi < xRight)
{
fBlue -= xInc;
fRed -= xInc;
}
else
{
fBlue += xInc;
fRed = 0;
}
}
/*
* Flush the framebuffer memory range to ensure changes are written to the
* actual memory, and therefore accessible by the VDMA.
*/
Xil_DCacheFlushRange((unsigned int) frame, DISPLAYDEMO_MAX_FRAME * 4);
break;
case DISPLAYDEMO_PATTERN_1:
wStride = stride / 4; /* Find the stride in 32-bit words */
xInt = width / 7; //Seven intervals, each with width/7 pixels
xInc = 256.0 / ((double) xInt); //256 color intensities per interval. Notice that overflow is handled for this pattern.
fColor = 0.0;
wCurrentInt = 1;
for(xcoi = 0; xcoi < width; xcoi++)
{
if (wCurrentInt & 0b001)
fRed = fColor;
else
fRed = 0.0;
if (wCurrentInt & 0b010)
fBlue = fColor;
else
fBlue = 0.0;
if (wCurrentInt & 0b100)
fGreen = fColor;
else
fGreen = 0.0;
/*
* Just draw white in the last partial interval (when width is not divisible by 7)
*/
if (wCurrentInt > 7)
{
wColor = 0x00FFFFFF;
}
else
{
wColor = ((u32) fRed << BIT_DISPLAY_RED) | ((u32) fBlue << BIT_DISPLAY_BLUE) | ( (u32) fGreen << BIT_DISPLAY_GREEN);
}
iPixelAddr = xcoi;
for(ycoi = 0; ycoi < height; ycoi++)
{
frame[iPixelAddr] = wColor;
/*
* This pattern is printed one vertical line at a time, so the address must be incremented
* by the stride instead of just 1.
*/
iPixelAddr += wStride;
}
fColor += xInc;
if (fColor >= 256.0)
{
fColor = 0.0;
wCurrentInt++;
}
}
/*
* Flush the framebuffer memory range to ensure changes are written to the
* actual memory, and therefore accessible by the VDMA.
*/
Xil_DCacheFlushRange((unsigned int) frame, DISPLAYDEMO_MAX_FRAME * 4);
break;
default :
xil_printf("Error: invalid pattern passed to DisplayDemoPrintTest");
}
}
XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
{
struct pbuf *q;
s32_t n_pbufs;
XEmacPs_Bd *txbdset, *txbd, *last_txbd = NULL;
XEmacPs_Bd *temp_txbd;
XStatus status;
XEmacPs_BdRing *txring;
u32_t bdindex;
u32_t lev;
lev = mfcpsr();
mtcpsr(lev | 0x000000C0);
txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
/* first count the number of pbufs */
for (q = p, n_pbufs = 0; q != NULL; q = q->next)
n_pbufs++;
/* obtain as many BD's */
status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset);
if (status != XST_SUCCESS) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
return XST_FAILURE;
}
for(q = p, txbd = txbdset; q != NULL; q = q->next) {
bdindex = XEMACPS_BD_TO_INDEX(txring, txbd);
if (tx_pbufs_storage[bdindex] != 0) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
return XST_FAILURE;
}
/* Send the data from the pbuf to the interface, one pbuf at a
time. The size of the data in each pbuf is kept in the ->len
variable. */
Xil_DCacheFlushRange((u32_t)q->payload, (u32_t)q->len);
XEmacPs_BdSetAddressTx(txbd, (u32)q->payload);
if (q->len > (XEMACPS_MAX_FRAME_SIZE - 18))
XEmacPs_BdSetLength(txbd, (XEMACPS_MAX_FRAME_SIZE - 18) & 0x3FFF);
else
XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
tx_pbufs_storage[bdindex] = (s32_t)q;
pbuf_ref(q);
last_txbd = txbd;
XEmacPs_BdClearLast(txbd);
txbd = XEmacPs_BdRingNext(txring, txbd);
}
XEmacPs_BdSetLast(last_txbd);
/* For fragmented packets, remember the 1st BD allocated for the 1st
packet fragment. The used bit for this BD should be cleared at the end
after clearing out used bits for other fragments. For packets without
just remember the allocated BD. */
temp_txbd = txbdset;
txbd = txbdset;
txbd = XEmacPs_BdRingNext(txring, txbd);
q = p->next;
for(; q != NULL; q = q->next) {
XEmacPs_BdClearTxUsed(txbd);
txbd = XEmacPs_BdRingNext(txring, txbd);
}
XEmacPs_BdClearTxUsed(temp_txbd);
status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset);
if (status != XST_SUCCESS) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
return XST_FAILURE;
}
/* Start transmit */
XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK));
mtcpsr(lev);
return status;
}
/**
*
* API to set high speed in card and host. Changes clock in host accordingly.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
{
s32 Status;
u32 StatusReg;
u32 Arg;
u32 ClockReg;
u16 BlkCnt;
u16 BlkSize;
u8 ReadBuff[64];
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->CardType == XSDPS_CARD_SD) {
BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
BlkSize &= XSDPS_BLK_SIZE_MASK;
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_BLK_SIZE_OFFSET, BlkSize);
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_XFER_MODE_OFFSET,
XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
Arg = XSDPS_SWITCH_CMD_HS_SET;
Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
/*
* Check for transfer complete
* Polling for response for now
*/
do {
StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET);
if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
/* Write to clear error bits */
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_ERR_INTR_STS_OFFSET,
XSDPS_ERROR_INTR_ALL_MASK);
Status = XST_FAILURE;
goto RETURN_PATH;
}
} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
/* Write to clear bit */
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
/* Change the clock frequency to 50 MHz */
InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
Arg = XSDPS_MMC_HIGH_SPEED_ARG;
Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
/*
* Check for transfer complete
*/
do {
StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET);
if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
/*
* Write to clear error bits
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_ERR_INTR_STS_OFFSET,
XSDPS_ERROR_INTR_ALL_MASK);
Status = XST_FAILURE;
goto RETURN_PATH;
}
} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
/*
* Write to clear bit
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
/* Change the clock frequency to 52 MHz */
InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
} else {
Arg = XSDPS_MMC_HS200_ARG;
Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
/*
* Check for transfer complete
*/
do {
StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET);
if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
/*
* Write to clear error bits
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_ERR_INTR_STS_OFFSET,
XSDPS_ERROR_INTR_ALL_MASK);
Status = XST_FAILURE;
goto RETURN_PATH;
}
} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
/*
* Write to clear bit
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
/* Change the clock frequency to 200 MHz */
InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XSdPs_Execute_Tuning(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
#if defined (__arm__) || defined (__aarch64__)
/* Program the Tap delays */
XSdPs_SetTapDelay(InstancePtr);
#endif
}
#if defined (__arm__) || defined (__aarch64__)
usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
#endif
#ifdef __MICROBLAZE__
/* 2 msec delay */
MB_Sleep(2);
#endif
StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET);
StatusReg |= XSDPS_HC_SPEED_MASK;
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_RESP0_OFFSET);
Status = XST_SUCCESS;
RETURN_PATH:
return Status;
}
int main()
{
int bufId = 0;
init_platform();
printf("Hello World\n\r");
if(i2c_init_clk() != XST_SUCCESS)
return -1;
// Actual test
// We'll allocate four packets on the heap
uint8_t* buf[4];
for(bufId = 0; bufId < 4; bufId++)
{
//buf[bufId] = malloc(TEST_PKT_SIZE);
buf[bufId] = memalign(8, TEST_PKT_SIZE);
if(buf[bufId] == 0)
printf("ERROR: Buffer %d allocation failed\r\n", bufId);
// Sanity check the alignment
if((uint32_t)buf[bufId] & 0x7)
{
printf("ERROR: Buffer %d allocated at %p has invalid alignment\r\n", bufId, buf[bufId]);
return -1;
}
}
uint8_t destMac[6] = {0x00, 0x11, 0x22, 0x33, 0x01, 0x00};
uint8_t srcMac[6] = {0x00, 0x11, 0x22, 0x33, 0x00, 0x00};
// First, set up the actual contents of those packets
for(bufId = 0; bufId < 4; bufId++)
{
int i = 0;
// Fill in the MAC addresses
for(i = 0; i < 6; i++)
{
buf[bufId][i] = destMac[i];
buf[bufId][i+6] = srcMac[i];
}
// Fill out the ethertype
buf[bufId][12] = 0x08;
buf[bufId][13] = 0x00;
memset(&buf[bufId][14], bufId+0xAA, TEST_PKT_SIZE - 14);
}
// Now fill in the bd descriptors
// Alloc the BD descriptors
XAxiDma_Bd* bd[4];
for(bufId = 0; bufId < 4; bufId++)
{
//bd[bufId] = malloc(sizeof(XAxiDma_Bd));
bd[bufId] = memalign(64, sizeof(XAxiDma_Bd));
if(bd[bufId] == 0)
printf("ERROR: Buffer BD descriptor %d allocation failed\r\n", bufId);
memset(bd[bufId], 0, sizeof(XAxiDma_Bd));
// Sanity check that they're aligned appropriately
// They need to be on a 16-word (i.e. 64-byte) boundary
if((uint32_t)bd[bufId] & 0x3F)
{
printf("ERROR: Buffer BD descriptor %d allocated at %p has invalid alignment\r\n", bufId, bd[bufId]);
return -1;
}
// Fill in the descriptor fields
//XAxiDma_BdSetBufAddr(bd[bufId], (uint32_t)buf[bufId]);
//XAxiDma_BdSetLength(bd[bufId], TEST_PKT_SIZE, DMA_BUF_MAX);
// Just do those manually - the driver appears to expect some metadata to be
// added by the ring manager, which we don't add ourselves.
XAxiDma_BdWrite(bd[bufId], XAXIDMA_BD_BUFA_OFFSET, (uint32_t)buf[bufId]);
XAxiDma_BdWrite(bd[bufId], XAXIDMA_BD_CTRL_LEN_OFFSET, TEST_PKT_SIZE);
// Need to set SOF and EOF bits too
// Do that manually - the API doesn't appear to expose it properly
// XAxiDma_Bd is actually an array behind the scenes, hence this syntax
uint32_t tmp = XAxiDma_BdRead(bd[bufId], XAXIDMA_BD_CTRL_LEN_OFFSET);
tmp |= (XAXIDMA_BD_CTRL_TXSOF_MASK | XAXIDMA_BD_CTRL_TXEOF_MASK);
XAxiDma_BdWrite(bd[bufId], XAXIDMA_BD_CTRL_LEN_OFFSET, tmp);
}
for(bufId = 0; bufId < 4; bufId++)
{
// Set the "next" descriptor pointers now everything has been allocated properly.
XAxiDma_BdWrite(bd[bufId], XAXIDMA_BD_NDESC_OFFSET, (uint32_t)(bd[(bufId + 1) % 4]));
// Debugging sanity check
XAxiDma_DumpBd(bd[bufId]);
}
// Buffers should now be set up
// Set up the DMA core and (hopefully) start!
// Flush caches to ensure that everything is coherent
for(bufId = 0; bufId < 4; bufId++)
{
XAXIDMA_CACHE_FLUSH(bd[bufId]);
// Also flush packets
// Syntax stolen from xaxidma_bd.h
Xil_DCacheFlushRange((uint32_t)buf[bufId], TEST_PKT_SIZE);
}
// First, reset the DMA core
uint32_t reg = 0;
reg = DMA_GET_REG(XAXIDMA_CR_OFFSET);
reg |= XAXIDMA_CR_RESET_MASK;
DMA_SET_REG(XAXIDMA_CR_OFFSET, reg);
while(DMA_GET_REG(XAXIDMA_CR_OFFSET) & XAXIDMA_CR_RESET_MASK);
printf("DMA Reset\r\n");
// Update the "next" pointer
DMA_SET_REG(XAXIDMA_CDESC_OFFSET, (uint32_t)bd[0]);
// The tail pointer should already be zero. Leave it.
// Enable cyclic BD mode
reg = DMA_GET_REG(XAXIDMA_CR_OFFSET);
reg |= XAXIDMA_CR_CYCLIC_MASK;
DMA_SET_REG(XAXIDMA_CR_OFFSET, reg);
// Set run mode!
reg = DMA_GET_REG(XAXIDMA_CR_OFFSET);
reg |= XAXIDMA_CR_RUNSTOP_MASK;
DMA_SET_REG(XAXIDMA_CR_OFFSET, reg);
// Quickly check we can read the base address from the ethernet...
printf("TEST: 0x%x\r\n", DMA_GET_REG(XAXIDMA_CR_OFFSET));
// Cyclic mode seems to require that we write something to the tail descriptor
DMA_SET_REG(XAXIDMA_TDESC_OFFSET, 0x0);
while(1)
{
volatile int x = 0;
uint32_t tmp = 0;
uint32_t tmpHigh = 0;
tmp = DMA_GET_REG(XAXIDMA_SR_OFFSET);
printf("DMA STATUS: 0x%x\r\n", tmp);
tmp = TENGIG_GET_REG(0x200); // LSW bytes recv
tmpHigh = TENGIG_GET_REG(0x204); // MSW bytes recv
printf("RX BYTES: 0x%x%x\r\n", tmpHigh, tmp);
tmp = TENGIG_GET_REG(0x208); // LSW bytes tx
tmpHigh = TENGIG_GET_REG(0x20C); // MSW bytes tx
printf("TX BYTES: 0x%x%x\r\n", tmpHigh, tmp);
tmp = TENGIG_GET_REG(0x2D8);
tmpHigh = TENGIG_GET_REG(0x2DC);
printf("TX OK: 0x%x%x\r\n", tmpHigh, tmp);
tmp = TENGIG_GET_REG(0x2E0);
tmpHigh = TENGIG_GET_REG(0x2E4);
printf("TX BROADCAST: 0x%x%x\r\n", tmpHigh, tmp);
tmp = TENGIG_GET_REG(0x2F0);
tmpHigh = TENGIG_GET_REG(0x2F4);
printf("TX UNDERRUN: 0x%x%x\r\n", tmpHigh, tmp);
tmp = DMA_GET_REG(0x8);
printf("CURDES: 0x%x\r\n", tmp);
printf("\r\n");
for(x = 0 ; x < 100000000; x++);
}
cleanup_platform();
return 0;
}
/*
*
* This function does one simple transfer
*
* @param InstancePtr is a pointer to the XAxiCdma instance
* @param Length is the transfer length
* @param Retries is how many times to retry on submission
*
* @return
* - XST_SUCCESS if transfer is successful
* - XST_FAILURE if either the transfer fails or the data has
* error.
*
* @note None.
*
******************************************************************************/
static int DoSimpleTransfer(XAxiCdma *InstancePtr, int Length, int Retries)
{
u32 Index;
u8 *SrcPtr;
u8 *DestPtr;
int Status;
Done = 0;
Error = 0;
/* Initialize the source buffer bytes with a pattern and the
* the destination buffer bytes to zero
*/
SrcPtr = (u8 *)SrcBuffer;
DestPtr = (u8 *)DestBuffer;
for (Index = 0; Index < Length; Index++) {
SrcPtr[Index] = Index & 0xFF;
DestPtr[Index] = 0;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)&SrcBuffer, Length);
/* Try to start the DMA transfer
*/
while (Retries) {
Retries -= 1;
Status = XAxiCdma_SimpleTransfer(InstancePtr, (u32)SrcBuffer,
(u32)DestBuffer, Length, Example_SimpleCallBack,
InstancePtr);
if (Status == XST_SUCCESS) {
break;
}
}
if (!Retries) {
xdbg_printf(XDBG_DEBUG_ERROR, "Submit transfer failed\r\n");
return XST_FAILURE;
}
/* Wait until the DMA transfer is done
*/
while (!Done && !Error) {
/* Wait */
}
if (Error) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Simple transfer has error %x\r\n",
(unsigned int)XAxiCdma_GetError(InstancePtr));
return XST_FAILURE;
}
/* Transfer completes successfully, check data
*/
Status = CheckData(SrcPtr, DestPtr, Length);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Check data failed for simple "
"transfer\r\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* This function transmits one packet non-blockingly through the DMA engine.
*
* @param AxiDmaInstPtr points to the DMA engine instance
*
* @return - XST_SUCCESS if the DMA accepts the packet successfully,
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
static int SendPacket(XAxiDma * AxiDmaInstPtr,int c)
{
XAxiDma_BdRing *TxRingPtr; //TxRing
cplx_data_t *TxPacket; //PacketPointer
//cplx_data_t *RxClean; //CleanData Do in RxSetup
XAxiDma_Bd *BdPtr; //Start BDPointer
int Status;
int Index;
char str[30];
TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
TxPacket = (cplx_data_t *)stim_buf; //setPointerForPacket
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN*64); //8 point each packet
int FreeBdCount = XAxiDma_BdRingGetFreeCnt(TxRingPtr);
xil_printf("TxFreeBdCount %d", FreeBdCount);
/* Allocate a BD */
Status = XAxiDma_BdRingAlloc(TxRingPtr, 32, &BdPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
xil_printf("check1");
XAxiDma_Bd *BdCurPtr;
u32 TxBufferPtr;
BdCurPtr = BdPtr; // Set Current BDptr
TxBufferPtr = (u32)stim_buf;
for (Index = 0; Index < 32; Index++) {
Status = XAxiDma_BdSetBufAddr(BdCurPtr, TxBufferPtr);
if (Status != XST_SUCCESS) {
xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
(unsigned int)TxBufferPtr, (unsigned int)BdCurPtr, Status);
return XST_FAILURE;
}
Status = XAxiDma_BdSetLength(BdCurPtr, MAX_PKT_LEN*4,
TxRingPtr->MaxTransferLen);
if (Status != XST_SUCCESS) {
xil_printf("Tx set length %d on BD %x failed %d\r\n",
MAX_PKT_LEN*4, (unsigned int)BdCurPtr, Status);
return XST_FAILURE;
}
#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
Status = XAxiDma_BdSetAppWord(BdCurPtr,
XAXIDMA_LAST_APPWORD, MAX_PKT_LEN*2);
/* If Set app length failed, it is not fatal
*/
if (Status != XST_SUCCESS) {
xil_printf("Set app word failed with %d\r\n", Status);
}
#endif
/* For single packet, both SOF and EOF are to be set
*/
XAxiDma_BdSetCtrl(BdCurPtr, XAXIDMA_BD_CTRL_TXEOF_MASK |
XAXIDMA_BD_CTRL_TXSOF_MASK);
XAxiDma_BdSetId(BdCurPtr, (u32) TxBufferPtr);
TxBufferPtr += MAX_PKT_LEN*4;
BdCurPtr = XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
}
/* Give the BD to DMA to kick off the transmission. */
Status = XAxiDma_BdRingToHw(TxRingPtr, 32, BdPtr);
if (Status != XST_SUCCESS) {
xil_printf("to hw failed %d\r\n", Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
* This function performs SD write in polled mode.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because another transfer
* is in progress or command or data inhibit is set
*
******************************************************************************/
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
{
s32 Status;
u32 PresentStateReg;
u32 StatusReg;
if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
!= XSDPS_CAPS_EMB_SLOT)) {
if(InstancePtr->Config.CardDetect != 0U) {
/* Check status to ensure card is initialized */
PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_PRES_STATE_OFFSET);
if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
}
}
/* Set block size to 512 if not already set */
if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
Status = XSdPs_SetBlkSize(InstancePtr,
XSDPS_BLK_SIZE_512_MASK);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
}
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_XFER_MODE_OFFSET,
XSDPS_TM_AUTO_CMD12_EN_MASK |
XSDPS_TM_BLK_CNT_EN_MASK |
XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
/* Send block write command */
Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
/*
* Check for transfer complete
* Polling for response for now
*/
do {
StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET);
if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
/* Write to clear error bits */
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_ERR_INTR_STS_OFFSET,
XSDPS_ERROR_INTR_ALL_MASK);
Status = XST_FAILURE;
goto RETURN_PATH;
}
} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
/* Write to clear bit */
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
Status = XST_SUCCESS;
RETURN_PATH:
return Status;
}
void pong(DisplayCtrl *video ,u32 uartAddress, XGpio *btn, XGpio *sw){
u32 height = video->vMode.height,
width = video->vMode.width,
stride = video->stride,
*frame,
speed = 2,
pause=false;
char entrada;
frame=video->framePtr[video->curFrame];
xil_printf("\x1B[H"); //Set cursor to top left of terminal
xil_printf("\x1B[2J"); //Clear terminal
Rectangulo bola=crearRectangulo(10,10,RED,ANCHO_BOLA,ALTO_BOLA);
Rectangulo palaIzquierda = crearRectangulo(0,height/2-ALTO_PALA/2,GREEN,ANCHO_PALA,ALTO_PALA);
Rectangulo palaDerecha = crearRectangulo(width-ANCHO_PALA,height/2-ALTO_PALA/2,GREEN,ANCHO_PALA,ALTO_PALA);
int dir_x=true, dir_y=true, indice_frame=0,salir=0,pulsar=0,puntuacionA=0,puntuacionB=0;
salir = XGpio_DiscreteRead(sw, 1);
while(salir & 0x8){
if (salir & 0x1) // 0x1=0b0001=posicion de SW0
bola.color = WHITE;
else
bola.color = RED;
//apunta a al siguente frame
indice_frame=nextFrame(video,&frame);
pintarFondo(frame, BLACK, width,height,stride);
//movimiento y colision
if(dir_x == DERECHA)
if ((bola.x+ANCHO_BOLA > palaDerecha.x) && (bola.y >= palaDerecha.y && bola.y < palaDerecha.y+ALTO_PALA )){
bola.x-=speed;
dir_x = IZQUIERDA;
}else{
bola.x+=speed;
}
else
if ((bola.x < palaIzquierda.x+ANCHO_PALA) && (bola.y >= palaIzquierda.y && bola.y < palaIzquierda.y+ALTO_PALA)){
bola.x+=speed;
dir_x = DERECHA;
}else{
bola.x-=speed;
}
if(dir_y == ABAJO)
bola.y+=speed;
else
bola.y-=speed;
//control de direccion
if (bola.x<0){
bola.x=width/2;
bola.y=height/2;
dir_x=DERECHA;
puntuacionB++;
xil_printf("%d - %d\n\r",puntuacionA,puntuacionB);
TimerDelay(1500000);
}else if(bola.x>width - ANCHO_BOLA){
bola.x=width/2;
bola.y=height/2;
dir_x=IZQUIERDA;
puntuacionA++;
xil_printf("%d - %d\n\r",puntuacionA,puntuacionB);
TimerDelay(1500000);
}
if (bola.y<0){
bola.y=0;
dir_y=ABAJO;
}else if(bola.y>height - ALTO_BOLA){
bola.y=height - ALTO_BOLA;
dir_y=ARRIBA;
}
//pintar la pelota y las palas
pintarRectangulo(frame,&bola,width,height,stride);
pintarRectangulo(frame,&palaDerecha,width,height,stride);
pintarRectangulo(frame,&palaIzquierda,width,height,stride);
//flush
Xil_DCacheFlushRange((unsigned int) frame, DISPLAY_MAX_FRAME * 4);
DisplayChangeFrame(video,indice_frame);
//TimerDelay(17000);
salir = XGpio_DiscreteRead(sw, 1);
pulsar = XGpio_DiscreteRead(btn, 1);
//control de las palas
if (pulsar & 0x1){ //Pala derecha
if (palaDerecha.y+ALTO_PALA < height){
palaDerecha.y+=speed;
}
}else if(pulsar & 0x2){
if (palaDerecha.y >= 0){
palaDerecha.y-=speed;
}
}
if (pulsar & 0x4 ){ //Pala izquierda
if (palaIzquierda.y+ALTO_PALA < height){
palaIzquierda.y+=speed;
}
}else if(pulsar & 0x8){
if (palaIzquierda.y >= 0){
palaIzquierda.y-=speed;
}
}
//recolocar las palas si se han salido fuera
if (palaDerecha.y<0)
palaDerecha.y=0;
else if (palaDerecha.y+ALTO_PALA>height)
palaDerecha.y=height-ALTO_PALA;
if (palaIzquierda.y<0)
palaIzquierda.y=0;
else if (palaIzquierda.y+ALTO_PALA>height)
palaIzquierda.y=height-ALTO_PALA;
//leer pulsaciones de cambio de velocidad
if (XUartPs_IsReceiveData(uartAddress)){
entrada=XUartPs_ReadReg(uartAddress, XUARTPS_FIFO_OFFSET);
if (entrada==' '){
pause=true;
while(pause){
if (XUartPs_IsReceiveData(uartAddress)){
entrada=XUartPs_ReadReg(uartAddress, XUARTPS_FIFO_OFFSET);
if (entrada==' ')
pause=false;
else
cambiarVelocidad(&speed,entrada);
}
}
}else
cambiarVelocidad(&speed,entrada);
}
}
}
volatile void *vbx_remap_uncached(void *p)
{
Xil_DCacheFlushRange((u32) p, 1);
return (volatile void *) VBX_UNCACHED_ADDR(p);
}
/**
* This main function starts the USB Intrerrupt example.
*
*
* @param None.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if test fails.
* @note None.
*
*****************************************************************************/
int main()
{
int Status;
int Index = 0;
int Cnt = 0;
/*
* Initialize the USB driver.
*/
UsbConfigPtr = XUsb_LookupConfig(USB_DEVICE_ID);
if (UsbConfigPtr == NULL) {
return XST_FAILURE;
}
#ifdef __PPC__
Xil_ICacheEnableRegion (0x80000001);
Xil_DCacheEnableRegion (0x80000001);
#endif
#ifdef __MICROBLAZE__
Xil_ICacheInvalidate();
Xil_ICacheEnable();
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
Status = XUsb_CfgInitialize(&UsbInstance,
UsbConfigPtr,
UsbConfigPtr->BaseAddress);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
/*
* Initialize the USB instance as required for the
* application.
*/
InitUsbInterface(&UsbInstance);
/*
* Set our function address to 0 which is the unenumerated state.
*/
Status = XUsb_SetDeviceAddress(&UsbInstance, 0);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
/*
* Setup the interrupt handlers.
*/
XUsb_IntrSetHandler(&UsbInstance, (void *) UsbIfIntrHandler,
&UsbInstance);
XUsb_EpSetHandler(&UsbInstance, 0,
(XUsb_EpHandlerFunc *) Ep0IntrHandler, &UsbInstance);
XUsb_EpSetHandler(&UsbInstance, 1,
(XUsb_EpHandlerFunc *) Ep1IntrHandler, &UsbInstance);
/*
* Setup the interrupt system.
*/
Status = SetupInterruptSystem(&UsbInstance);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupts.
*/
XUsb_IntrEnable(&UsbInstance, XUSB_STATUS_GLOBAL_INTR_MASK |
XUSB_STATUS_RESET_MASK |
XUSB_STATUS_SUSPEND_MASK |
XUSB_STATUS_DISCONNECT_MASK |
XUSB_STATUS_FIFO_BUFF_RDY_MASK |
XUSB_STATUS_FIFO_BUFF_FREE_MASK |
XUSB_STATUS_EP0_BUFF1_COMP_MASK |
XUSB_STATUS_EP1_BUFF1_COMP_MASK |
XUSB_STATUS_EP2_BUFF1_COMP_MASK |
XUSB_STATUS_EP1_BUFF2_COMP_MASK |
XUSB_STATUS_EP2_BUFF2_COMP_MASK);
XUsb_Start(&UsbInstance);
/*
* Set the device configuration to unenumerated state.
*/
UsbInstance.DeviceConfig.CurrentConfiguration = 0;
/*
* Wait untill the USB device is enumerated.
*/
while (!UsbInstance.DeviceConfig.CurrentConfiguration);
/*
* Stop the test if the Stop key is pressed or
* device lost enumeration.
*/
while (1) {
if (UsbInstance.Config.DmaEnabled) {
/* Flush the cache before DMA transfer */
Xil_DCacheFlushRange((u32)&Hello_wav[Index],(u32)1024);
}
if (XUsb_EpDataSend(&UsbInstance, 1, &Hello_wav[Index],
1024) == XST_SUCCESS){
Index += 1024;
Cnt ++;
if (Cnt >= 9000){
Cnt =0;
Index = 0;
}
}
}
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the interrupt test. It does the following:
* Set up the output terminal if UART16550 is in the hardware build
* Initialize the DMA engine
* Set up Tx and Rx channels
* Set up the interrupt system for the Tx and Rx interrupts
* Submit a transfer
* Wait for the transfer to finish
* Check transfer status
* Disable Tx and Rx interrupts
* Print test status and exit
*
* @param None
*
* @return
* - XST_SUCCESS if example finishes successfully
* - XST_FAILURE if example fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
int Tries = NUMBER_OF_TRANSFERS;
int Index;
u8 *TxBufferPtr;
u8 *RxBufferPtr;
u8 Value;
TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
RxBufferPtr = (u8 *)RX_BUFFER_BASE;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(XAxiDma_HasSg(&AxiDma)){
xil_printf("Device configured as SG mode \r\n");
return XST_FAILURE;
}
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
/* Disable all interrupts before setup */
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Enable all interrupts */
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
Value = TEST_START_VALUE;
for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
TxBufferPtr[Index] = Value;
Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN);
#endif
/* Send a packet */
for(Index = 0; Index < Tries; Index ++) {
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (!TxDone && !RxDone && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN, 0xC);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
xil_printf("AXI DMA interrupt example test passed\r\n");
/* Disable TX and RX Ring interrupts and return success */
DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
Done:
xil_printf("--- Exiting main() --- \r\n");
return XST_SUCCESS;
}
int main(void) {
xil_printf("Starting\r\n");
int Status;
int i;
u32 start_time;
u32 end_time;
u32 return_val[ACTUAL_READS];
// Initialize DMA
Status = DMA_init(DMA_DEV_ID);
if (Status != XST_SUCCESS) {
xil_printf("XAxiDma_init: Failed %d\r\n", Status);
return XST_FAILURE;
}
// Initialize PE
Status = XNeedlemanwunsch_Initialize(&PE, PE_DEV_ID);
if (Status != XST_SUCCESS) {
xil_printf("XNeedlemanwunsch_Initialize: Failed %d\r\n", Status);
return XST_FAILURE;
}
XNeedlemanwunsch_DisableAutoRestart(&PE);
// Initialize timer with maximum value so we can see how far down it
// goes. It should last about 12 seconds before hitting zero.
Timer_init(TIMER_DEV_ID);
XScuTimer_LoadTimer(&Timer, TIMER_MAX);
XScuTimer_SetPrescaler(&Timer, TIMER_PRESCALE-1);
start_time = TIMER_MAX;
// Flush caches
Xil_DCacheFlushRange((INTPTR)&ref_genome, sizeof(ref_genome));
XScuTimer_Start(&Timer);
for (i=0; i<ACTUAL_READS; i++) {
DMA_send();
writeRead(0, i);
while(!XNeedlemanwunsch_IsIdle(&PE) && !XNeedlemanwunsch_IsReady(&PE)) {
xil_printf("Waiting for idle/ready\r\n");
}
XNeedlemanwunsch_Start(&PE);
//if (XNeedlemanwunsch_IsIdle(&PE) || XNeedlemanwunsch_IsReady(&PE)) {
//xil_printf("Is still idle/ready\r\n");
//}
while(!XNeedlemanwunsch_IsDone(&PE) /*&& !XNeedlemanwunsch_IsIdle(&PE) && !XNeedlemanwunsch_IsReady(&PE)*/) {
}
return_val[i] = XNeedlemanwunsch_Get_return(&PE);
}
XScuTimer_Stop(&Timer);
end_time = XScuTimer_GetCounterValue(&Timer);
xil_printf("Done\r\n");
for (i=0; i<ACTUAL_READS; i++) {
xil_printf("read %d best fit at %d\r\n", i, return_val[i]);
}
print_time(start_time, end_time);
return 0;
}
