static int SetupInterruptSystem(XScuGic *GicInstancePtr, XScuTimer *TimerInstancePtr, u16 TimerIntrId)
{
XScuGic_Config *IntcConfig; //GIC config
Xil_ExceptionInit();
//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, TimerIntrId,
(Xil_ExceptionHandler)TimerIntrHandler,
(void *)TimerInstancePtr);
//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, TimerIntrId);
//enable interrupt on the timer
XScuTimer_EnableInterrupt(TimerInstancePtr);
// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
/**
* This function sets up the interrupt system so interrupts can occur for the
* CSU DMA. This function is application-specific. The user should modify this
* function to fit the application.
*
* @param IntcInstancePtr is a pointer to the instance of the INTC.
* @param InstancePtr contains a pointer to the instance of the CSU DMA
* driver which is going to be connected to the interrupt
* controller.
* @param IntrId is the interrupt Id and is typically
* XPAR_<CSUDMA_instance>_INTR value from xparameters.h.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE if failed
*
* @note None.
*
****************************************************************************/
static int SetupInterruptSystem(XScuGic *IntcInstancePtr,
XCsuDma *InstancePtr,
u16 IntrId)
{
int Status;
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig; /* Config for interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTG_INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the
* hardware interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler,
IntcInstancePtr);
#endif
/*
* Connect a device driver handler that will be called when an
* interrupt for the device occurs, the device driver handler
* performs the specific interrupt processing for the device
*/
Status = XScuGic_Connect(IntcInstancePtr, IntrId,
(Xil_ExceptionHandler) IntrHandler,
(void *) InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the device
*/
XScuGic_Enable(IntcInstancePtr, IntrId);
/*
* Enable interrupts
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
void platform_enable_interrupts()
{
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
XScuTimer_EnableInterrupt(&TimerInstance);
XScuTimer_Start(&TimerInstance);
}
void platform_enable_interrupts()
{
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
XTtcPs_EnableInterrupts(&TimerInstance, XTTCPS_IXR_INTERVAL_MASK);
XTtcPs_Start(&TimerInstance);
return;
}
/**
*
* This function setups the interrupt system such that interrupts can occur for
* the USB controller. This function is application specific since the actual
* system may or may not have an interrupt controller. The USB controller could
* be directly connected to a processor without an interrupt controller. The
* user should modify this function to fit the application.
*
* @param IntcInstancePtr is a pointer to instance of the Intc controller.
* @param UsbInstancePtr is a pointer to instance of the USB controller.
* @param UsbIntrId is the Interrupt Id and is typically
* XPAR_<INTC_instance>_<USB_instance>_VEC_ID value
* from xparameters.h
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE on error
*
******************************************************************************/
static int UsbSetupIntrSystem(XScuGic *IntcInstancePtr,
XUsbPs *UsbInstancePtr, u16 UsbIntrId)
{
int Status;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Xil_ExceptionInit();
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, UsbIntrId,
(Xil_ExceptionHandler)XUsbPs_IntrHandler,
(void *)UsbInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the device.
*/
XScuGic_Enable(IntcInstancePtr, UsbIntrId);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
static int gpio_setupInts(audioPlayer_t *pThis) {
// pointer to driver structure
XScuGic *pGIC;
// get pointer to GIC (already initialized at OS startup
pGIC = prvGetInterruptControllerInstance();
// connect own interrupt handler to GIC handler
XScuGic_Connect(pGIC, GPIO_INTERRUPT_ID,
(Xil_ExceptionHandler) gpio_intrHandler,(void *) pThis);
// Enable interrupt at GIC
XScuGic_Enable(pGIC, GPIO_INTERRUPT_ID);
/* Enable IRQ at core (should be enabled anyway)*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/* Enable IRQ in processor core */
return XST_SUCCESS;
}
int cortexa9_init(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(0);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)0);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
PROFILE_TIMER_INTR_ID,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/*
* Initialize the timer with Timer Ticks
*/
scu_timer_init() ;
Xil_ExceptionEnable();
return 0;
}
static void SetupInterruptSystem(XScuGic *GicInstancePtr, u32 *FPGAPtr, u16 FPGAIntrId,
XGpioPs *Gpio, u16 GpioIntrId)
{
XScuGic_Config *IntcConfig; //GIC config
Xil_ExceptionInit();
//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, FPGAIntrId,
(Xil_ExceptionHandler)FPGAIntrHandler,
(void *)FPGAPtr);
//set up the GPIO interrupt
XScuGic_Connect(GicInstancePtr, GpioIntrId,
(Xil_ExceptionHandler)XGpioPs_IntrHandler,
(void *)Gpio);
//Enable interrupts for all the pins in bank 0.
XGpioPs_SetIntrTypePin(Gpio, pbsw, XGPIOPS_IRQ_TYPE_EDGE_RISING);
//Set the handler for gpio interrupts.
XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, GPIOIntrHandler);
//Enable the GPIO interrupts of Bank 0.
XGpioPs_IntrEnablePin(Gpio, pbsw);
//Enable the interrupt for the GPIO device.
XScuGic_Enable(GicInstancePtr, GpioIntrId);
//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, FPGAIntrId);
// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
printf("Interrupt Set Up\n\r");
}
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, DEC and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
/* Init FIFO interrupt */
int audioRxTx_start(audioRxTx_t *pThis)
{
/* initialize interrupt handler */
XScuGic *pGic; // pointer to GIC interrupt driver
pGic = prvGetInterruptControllerInstance(); // retrieve pointer to initialized instance
// connect FIFO interrupt handler
XScuGic_Connect(pGic, XPS_FPGA15_INT_ID, (Xil_ExceptionHandler) audioRxTx_isr, (void*) pThis);
// enable IRQ interrupt at GIC
XScuGic_Enable(pGic, XPS_FPGA15_INT_ID);
// define priority and trigger type for AXI Stream FIFO IRQ
XScuGic_SetPriorityTriggerType(pGic, XPS_FPGA15_INT_ID, 0xA0, 0x3);
/* Enable IRQ in processor core */
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return 1;
}
/**
*
* This function sets up the interrupt system for the example. It enables falling
* edge interrupts for all the pins of bank 0 in the GPIO device.
*
* @param GicInstancePtr is a pointer to the XScuGic driver Instance.
* @param GpioInstancePtr contains a pointer to the instance of the GPIO
* component which is going to be connected to the interrupt
* controller.
* @param GpioIntrId is the interrupt Id and is typically
* XPAR_<GICPS>_<GPIOPS_instance>_VEC_ID value from
* xparameters.h.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
****************************************************************************/
static int SetupInterruptSystem(XScuGic *GicInstancePtr, XGpioPs *Gpio,
u16 GpioIntrId)
{
int Status;
XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */
Xil_ExceptionInit();
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(GicInstancePtr, GpioIntrId,
(Xil_ExceptionHandler)XGpioPs_IntrHandler,
(void *)Gpio);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable falling edge interrupts for all the pins in bank 0.
*/
XGpioPs_SetIntrType(Gpio, INPUT_BANK, 0x00, 0x00, 0x00);
/*
* Set the handler for gpio interrupts.
*/
XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, IntrHandler);
/*
* Enable the GPIO interrupts of Bank 0.
*/
XGpioPs_IntrEnable(Gpio, INPUT_BANK, 0xFFFFFFFF);
/*
* Enable the interrupt for the GPIO device.
*/
XScuGic_Enable(GicInstancePtr, GpioIntrId);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
void sys_irq_restore_enable(unsigned int flags)
{
Xil_ExceptionEnableMask(~flags);
}
/*
* Initialize Timer Interrupt
* In: interrupt frequency in Hz
*/
int initTmrInt(u32 int_freq) {
//Variables
int status;
u32 reset_val;
XScuGic_Config* IntcConfig;
//Timer
//Initialize Timer Controller
status = XTmrCtr_Initialize(&tmrCtr, TMR_DEVICE_ID);
if (status != XST_SUCCESS) {
return XST_FAILURE;
}
//Set Interrupt Handler for Timer Controller
XTmrCtr_SetHandler(&tmrCtr, (XTmrCtr_Handler) tmrIntrHandler, &tmrCtr);
//Reset Timer Value
int_freq = (u32) (FPGA_FREQ / int_freq);
reset_val = ~int_freq;
//Reset Timer Value
XTmrCtr_SetResetValue(&tmrCtr, 0, reset_val);
//Set Options
XTmrCtr_SetOptions(&tmrCtr, 0, TMR_OPTIONS);
//GIC
//Initialize Xil Exceptions
Xil_ExceptionInit();
//Initialize GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
status = XScuGic_CfgInitialize(&Intc, IntcConfig,
IntcConfig->CpuBaseAddress);
if (status != XST_SUCCESS) {
myprintf("mpu_utils.c: Error initializing SCU GIC Config.\r\n");
return XST_FAILURE;
}
//Connect interrupt controller interrupt handler to HW interrupt handling logic in PS
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler, &Intc);
//Connect driver handler (GIC) called when interrupt occurs to HW defined above
XScuGic_Connect(&Intc, INTC_TMR_INT_ID,
(Xil_ExceptionHandler) XTmrCtr_InterruptHandler, (void*) &tmrCtr);
//Set Callback Handler for Timer Interrupts
XTmrCtr_SetHandler(&tmrCtr, (XTmrCtr_Handler) tmrIntrHandler, &tmrCtr);
//Enable Timer Interrupts
XTmrCtr_EnableIntr(tmrCtr.BaseAddress, 0);
//Enable Interrupts for Timer
XScuGic_Enable(&Intc, INTC_TMR_INT_ID);
//Enable Interrupts in Processor
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
//Start Timer
XTmrCtr_Start(&tmrCtr, 0);
//Return
return XST_SUCCESS;
}
/*
* Set Up Interrupt for IMU
*/
int setupDMPInt() {
//Variables
int status;
XScuGic_Config* IntcConfig;
XGpioPs_Config* GpioConfig;
unsigned char data;
//MPU and DMP
//Configure MPU Interrupt Pin
status = imuReadIntConfig(&data); //Read Register
if (status != XST_SUCCESS) {
return status;
}
//Modify Bits
data &= (~INT_LEVEL_BIT); //Clear bit --> active high
data &= (~INT_OPEN_BIT); //Clear bit --> push-pull
data &= (~INT_RD_CLEAR_BIT); //Clear bit --> interrupt status bits are cleared only by reading INT_STATUS (Register 58)
data |= LATCH_INT_EN_BIT; //Set bit --> INT pin is held high until the interrupt is cleared
//Configure Int Pin
status = imuConfigureInt(&data);
if (status != XST_SUCCESS) {
return status;
}
//Set Interrupt level
status = mpu_set_int_level(0); //Set Interrupt for "active high" (0)
if (status != XST_SUCCESS) {
myprintf("mpu_int.c: Could not set interrupt level.\r\n");
return status;
}
//Enable Latched Interrupt
status = imuSetIntLatched(1);
if (status != XST_SUCCESS) {
myprintf("mpu_int.c: Could not set latched interrupt.\r\n");
return status;
}
//Set DMP Interrupt Mode
status = imuSetDmpIntMode(DMP_INT_CONTINUOUS); //Interrupt when one FIFO period has elapsed
if (status != XST_SUCCESS) {
myprintf("mpu_int.c: Could not set interrupt mode.\r\n");
return status;
}
//Initialize Xil Exceptions
Xil_ExceptionInit();
//Initialize GPIO
GpioConfig = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
status = XGpioPs_CfgInitialize(&Gpio, GpioConfig, GpioConfig->BaseAddr);
if (status != XST_SUCCESS) {
myprintf("mpu_utils.c: Error initializing GPIO Config.\r\n");
return status;
}
//Initialize GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
status = XScuGic_CfgInitialize(&Intc, IntcConfig,
IntcConfig->CpuBaseAddress);
if (status != XST_SUCCESS) {
myprintf("mpu_utils.c: Error initializing SCU GIC Config.\r\n");
return status;
}
//Connect interrupt controller interrupt handler to HW interrupt handling logic in PS
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler, &Intc);
//Connect driver handler (GIC) called when interrupt occurs to HW defined above
XScuGic_Connect(&Intc, GPIO_INT_ID,
(Xil_ExceptionHandler) myXGpioPs_IntrHandler, (void*) &Gpio); //Use my own Intr Handler
//Enable Interrupt for Pin
XGpioPs_SetIntrTypePin(&Gpio, GPIO_INT_PIN, XGPIOPS_IRQ_TYPE_EDGE_RISING);
//Set Callback Handler for GPIO Interrupts
XGpioPs_SetCallbackHandler(&Gpio, (void *) &Gpio,
(XGpioPs_Handler) ImuIntrHandler);
//Enable GPIO Interrupt for Pin
XGpioPs_IntrEnablePin(&Gpio, GPIO_INT_PIN);
if (!XGpioPs_IntrGetEnabledPin(&Gpio, GPIO_INT_PIN)) {
myprintf("mpu_int.c: Interrupt not enabled.\r\n");
}
//Enable Interrupts for GPIO
XScuGic_Enable(&Intc, GPIO_INT_ID);
//Enable Interrupts in Processor
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
//Free memory
return XST_SUCCESS;
}
