void start_adc_pwm(){
//Enable ADC and interrupts
__HAL_ADC_ENABLE(&hadc2);
//Warp field stabilize.
osDelay(2);
__HAL_ADC_ENABLE_IT(&hadc2, ADC_IT_JEOC);
//Init PWM
int half_load = htim1.Instance->ARR/2;
htim1.Instance->CCR1 = half_load;
htim1.Instance->CCR2 = half_load;
htim1.Instance->CCR3 = half_load;
//This hardware obfustication layer really is getting on my nerves
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_1);
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2);
HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_2);
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);
HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_3);
htim1.Instance->CCR4 = 1;
HAL_TIM_PWM_Start_IT(&htim1, TIM_CHANNEL_4);
//Turn off output
//__HAL_TIM_MOE_DISABLE(&htim1);
}
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t function = (uint32_t)NC;
// ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...)
// are described in PinNames.h and PeripheralPins.c
// Pin value must be between 0xF0 and 0xFF
if ((pin < 0xF0) || (pin >= 0x100)) {
// Normal channels
// Get the peripheral name from the pin and assign it to the object
obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
// Get the functions (adc channel) from the pin and assign it to the object
function = pinmap_function(pin, PinMap_ADC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
} else {
// Internal channels
obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
function = pinmap_function(pin, PinMap_ADC_Internal);
// No GPIO configuration for internal channels
}
MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
MBED_ASSERT(function != (uint32_t)NC);
obj->channel = STM_PIN_CHANNEL(function);
// Save pin number for the read function
obj->pin = pin;
// Configure ADC object structures
obj->handle.State = HAL_ADC_STATE_RESET;
obj->handle.Init.OversamplingMode = DISABLE;
obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1;
obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
obj->handle.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5;
obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
obj->handle.Init.ContinuousConvMode = DISABLE;
obj->handle.Init.DiscontinuousConvMode = DISABLE;
obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIG_EDGE_NONE;
obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
obj->handle.Init.DMAContinuousRequests = DISABLE;
obj->handle.Init.EOCSelection = EOC_SINGLE_CONV;
obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN;
obj->handle.Init.LowPowerAutoWait = ENABLE;
obj->handle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
obj->handle.Init.LowPowerAutoPowerOff = DISABLE;
__HAL_RCC_ADC1_CLK_ENABLE();
if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC");
}
if (!HAL_ADCEx_Calibration_GetValue(&obj->handle, ADC_SINGLE_ENDED)) {
HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
}
__HAL_ADC_ENABLE(&obj->handle);
}
/**
* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
uint16_t i = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
hadc->Instance->CR2 |= ADC_CR2_DMA;
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay inserted to wait during Tstab time the ADC's stabilazation */
for(; i <= 540; i++)
{
__NOP();
}
}
/* if no external trigger present enable software conversion of regular channels */
if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= ADC_CR2_SWSTART;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
hadc->Instance->CR2 |= ADC_CR2_DMA;
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) {
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while (counter != 0) {
counter--;
}
}
/* if no external trigger present enable software conversion of regular channels */
if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) {
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= ADC_CR2_SWSTART;
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables ADC and starts conversion of the regular channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Check if an injected conversion is ongoing */
if (hadc->State == HAL_ADC_STATE_BUSY_INJ) {
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
} else {
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
}
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) {
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while (counter != 0) {
counter--;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Check if Multimode enabled */
if (HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) {
/* if no external trigger present enable software conversion of regular channels */
if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) {
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
} else {
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) {
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
/* Return function status */
return HAL_OK;
}
void test_adc_trigger() {
//Set trigger to mid phase to check for trigger polarity
htim1.Instance->CCR4 = 2048;
HAL_TIM_PWM_Start_IT(&htim1, TIM_CHANNEL_4);
__HAL_ADC_ENABLE(&hadc2);
//Warp field stabilize.
osDelay(2);
__HAL_ADC_ENABLE_IT(&hadc2, ADC_IT_JEOC);
}
/**
* @brief Enables the selected ADC software start conversion of the injected channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0;
uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
/* Check if a regular conversion is ongoing */
if (hadc->State == HAL_ADC_STATE_BUSY_REG) {
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
} else {
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ;
}
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) {
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while (counter != 0) {
counter--;
}
}
/* Check if Multimode enabled */
if (HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) {
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if (tmp1 && tmp2) {
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
} else {
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if ((hadc->Instance == ADC1) && tmp1 && tmp2) {
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
uint16_t AdcMcuRead( Adc_t *obj, uint8_t channel )
{
ADC_HandleTypeDef *hadc;
ADC_ChannelConfTypeDef adcConf;
uint16_t adcData = 0;
hadc = &obj->Adc;
/* Enable HSI */
__HAL_RCC_HSI_ENABLE();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
}
__HAL_RCC_ADC1_CLK_ENABLE( );
adcConf.Channel = channel;
adcConf.Rank = ADC_REGULAR_RANK_1;
adcConf.SamplingTime = ADC_SAMPLETIME_192CYCLES;
HAL_ADC_ConfigChannel( hadc, &adcConf);
/* Enable ADC1 */
__HAL_ADC_ENABLE( hadc) ;
/* Start ADC1 Software Conversion */
HAL_ADC_Start( hadc);
HAL_ADC_PollForConversion( hadc, HAL_MAX_DELAY );
adcData = HAL_ADC_GetValue ( hadc);
__HAL_ADC_DISABLE( hadc) ;
if( ( adcConf.Channel == ADC_CHANNEL_TEMPSENSOR ) || ( adcConf.Channel == ADC_CHANNEL_VREFINT ) )
{
HAL_ADC_DeInit( hadc );
}
__HAL_RCC_ADC1_CLK_DISABLE( );
/* Disable HSI */
__HAL_RCC_HSI_DISABLE();
return adcData;
}
/* ADC2 init function */
void MX_ADC2_Init(void) {
ADC_ChannelConfTypeDef sConfig;
__HAL_RCC_ADC2_CLK_ENABLE();
// HAL_ADC_DeInit(&hadc2);
// hadc2.Instance->CR2 = 0;
/**Common config
*/
hadc2.Instance = ADC2;
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
hadc2.Init.ContinuousConvMode = DISABLE;
hadc2.Init.DiscontinuousConvMode = DISABLE;
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc2.Init.NbrOfConversion = 5;
HAL_ADC_Init(&hadc2);
sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
sConfig.Channel = ADC_CHANNEL_15;
sConfig.Rank = 1;
HAL_ADC_ConfigChannel(&hadc2, &sConfig);
sConfig.Channel = ADC_CHANNEL_13;
sConfig.Rank = 2;
HAL_ADC_ConfigChannel(&hadc2, &sConfig);
sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5;
sConfig.Channel = ADC_CHANNEL_10;
sConfig.Rank = 3;
HAL_ADC_ConfigChannel(&hadc2, &sConfig);
sConfig.Channel = ADC_CHANNEL_2;
sConfig.Rank = 4;
HAL_ADC_ConfigChannel(&hadc2, &sConfig);
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = 5;
HAL_ADC_ConfigChannel(&hadc2, &sConfig);
hadc2.Instance->CR2 |= ADC_CR2_DMA;
__HAL_ADC_ENABLE(&hadc2);
}
/**
* @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
*
* @note Caution: This function must be used only with the ADC master.
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
/* Process locked */
__HAL_LOCK(hadc);
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
}
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables the interrupt and starts ADC conversion of injected channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
/* - Set state bitfield related to injected operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
/* Check if a regular conversion is ongoing */
/* Note: On this device, there is no ADC error code fields related to */
/* conversions on group injected only. In case of conversion on */
/* going on group regular, no error code is reset. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables the interrupt and starts ADC conversion of injected channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
uint32_t i = 0, tmp1 = 0, tmp2 =0;
/* Process locked */
__HAL_LOCK(hadc);
/* Check if a regular conversion is ongoing */
if(hadc->State == HAL_ADC_STATE_BUSY_REG)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ;
}
/* Set ADC error code to none */
hadc->ErrorCode = HAL_ADC_ERROR_NONE;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay inserted to wait during Tstab time the ADC's stabilazation */
for(; i <= 540; i++)
{
__NOP();
}
}
/* Enable the ADC end of conversion interrupt for injected group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Enable the ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
void MX_ADC1_Init(void) {
ADC_MultiModeTypeDef multimode;
ADC_ChannelConfTypeDef sConfig;
__HAL_RCC_ADC1_CLK_ENABLE();
hadc1.Instance = ADC1;
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T8_TRGO;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.NbrOfConversion = 5;
HAL_ADC_Init(&hadc1);
/**Enable or disable the remapping of ADC1_ETRGREG:
* ADC1 External Event regular conversion is connected to TIM8 TRG0
*/
__HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE();
/**Configure the ADC multi-mode
*/
multimode.Mode = ADC_DUALMODE_REGSIMULT;
HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode);
sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
sConfig.Channel = ADC_CHANNEL_14;
sConfig.Rank = 1;
HAL_ADC_ConfigChannel(&hadc1, &sConfig);
sConfig.Channel = ADC_CHANNEL_0;
sConfig.Rank = 2;
HAL_ADC_ConfigChannel(&hadc1, &sConfig);
sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5;
sConfig.Channel = ADC_CHANNEL_11;
sConfig.Rank = 3;
HAL_ADC_ConfigChannel(&hadc1, &sConfig);
sConfig.Channel = ADC_CHANNEL_12;
sConfig.Rank = 4;
HAL_ADC_ConfigChannel(&hadc1, &sConfig);
sConfig.Channel = ADC_CHANNEL_12;
sConfig.Rank = 5;
HAL_ADC_ConfigChannel(&hadc1, &sConfig);
hadc1.Instance->CR2 |= ADC_CR2_DMA;
__HAL_ADC_ENABLE(&hadc1);
__HAL_RCC_DMA1_CLK_ENABLE();
DMA1_Channel1->CCR = 0;
DMA1_Channel1->CNDTR = 5;
DMA1_Channel1->CPAR = (uint32_t) & (ADC1->DR);
DMA1_Channel1->CMAR = (uint32_t)&adc_buffer;
DMA1_Channel1->CCR = DMA_CCR_MSIZE_1 | DMA_CCR_PSIZE_1 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_TCIE;
DMA1_Channel1->CCR |= DMA_CCR_EN;
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
}
/**
* @brief Enables the interrupt and starts ADC conversion of regular channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
uint16_t i = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Check if an injected conversion is ongoing */
if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
}
/* Set ADC error code to none */
hadc->ErrorCode = HAL_ADC_ERROR_NONE;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay inserted to wait during Tstab time the ADC's stabilazation */
for(; i <= 540; i++)
{
__NOP();
}
}
/* Enable the ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable the ADC end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
/* if no externel trigger present enable software conversion of regular channels */
if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if ((hadc->Instance == (ADC_TypeDef*)0x40012000) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}