/**
* \brief Update MPU regions.
*
* \return Unused (ANSI-C compatibility).
*/
void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
uint32_t dwRegionAttr)
{
/* Raise privilege, the MPU register could be set only in privilege mode */
asm volatile(" swi 0x00 ");
while (!dwRaisePriDone);
dwRaisePriDone = 0;
/* Disable interrupt */
__disable_irq();
/* Clean up data and instruction buffer */
__DSB();
__ISB();
/* Set active region */
MPU_SetRegionNum(dwRegionNum);
/* Disable region */
MPU_DisableRegion();
/* Update region attribute */
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/* Clean up data and instruction buffer to make the new region taking
effect at once */
__DSB();
__ISB();
/* Enable the interrupt */
__enable_irq();
/* Reset to thread mode */
__set_CONTROL(USER_MODE);
}
/**
\brief Test case: TC_CoreFunc_GetCtrl
\details
- Check if __set_CONTROL and __get_CONTROL() sets/gets control register
*/
void TC_CoreFunc_Control (void) {
// don't use stack for this variables
static uint32_t orig;
static uint32_t ctrl;
static uint32_t result;
orig = __get_CONTROL();
ctrl = orig;
result = UINT32_MAX;
#ifdef CONTROL_SPSEL_Msk
// toggle SPSEL
ctrl = (ctrl & ~CONTROL_SPSEL_Msk) | (~ctrl & CONTROL_SPSEL_Msk);
#endif
__set_CONTROL(ctrl);
__ISB();
result = __get_CONTROL();
__set_CONTROL(orig);
__ISB();
ASSERT_TRUE(result == ctrl);
ASSERT_TRUE(__get_CONTROL() == orig);
}
/**
* \brief Update MPU regions.
*
* \return Unused (ANSI-C compatibility).
*/
void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr)
{
/* Disable interrupt */
__disable_irq();
/* Clean up data and instruction buffer */
__DSB();
__ISB();
/* Set active region */
mpu_set_region_num(dw_region_num);
/* Disable region */
mpu_disable_region();
/* Update region attribute */
mpu_set_region( dw_region_base_addr, dw_region_attr);
/* Clean up data and instruction buffer to make the new region taking
effect at once */
__DSB();
__ISB();
/* Enable the interrupt */
__enable_irq();
}
void nOS_SwitchContext (void)
{
#if (NOS_CONFIG_MAX_UNSAFE_ISR_PRIO > 0)
nOS_StatusReg sr = __get_BASEPRI();
#endif
/* Request context switch */
*(volatile uint32_t *)0xE000ED04UL = 0x10000000UL;
/* Leave critical section */
#if (NOS_CONFIG_MAX_UNSAFE_ISR_PRIO > 0)
__set_BASEPRI(0);
#else
__enable_interrupt();
#endif
__DSB();
__ISB();
__no_operation();
/* Enter critical section */
#if (NOS_CONFIG_MAX_UNSAFE_ISR_PRIO > 0)
__set_BASEPRI(sr);
#else
__disable_interrupt();
#endif
__DSB();
__ISB();
}
/**
* \brief Update MPU regions.
*
* \return Unused (ANSI-C compatibility).
*/
void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
uint32_t dwRegionAttr)
{
/* Disable interrupt */
__disable_irq();
/* Clean up data and instruction buffer */
__DSB();
__ISB();
/* Set active region */
MPU_SetRegionNum(dwRegionNum);
/* Disable region */
MPU_DisableRegion();
/* Update region attribute */
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* Clean up data and instruction buffer to make the new region taking
effect at once */
__DSB();
__ISB();
/* Enable the interrupt */
__enable_irq();
}
__STATIC_INLINE void TCM_Enable(void)
{
__DSB();
__ISB();
SCB->ITCMCR = (SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk);
SCB->DTCMCR = (SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk);
__DSB();
__ISB();
}
__STATIC_INLINE void TCM_Disable(void)
{
__DSB();
__ISB();
SCB->ITCMCR &= ~((uint32_t) SCB_ITCMCR_EN_Msk);
SCB->DTCMCR &= ~((uint32_t) SCB_ITCMCR_EN_Msk);
__DSB();
__ISB();
}
/*!
\brief C part of the SVC exception handler
SVC 0 is initializing the OS and starting the scheduler.
Each thread stack frame is initialized.
\param svc_args Used to extract the SVC number
*/
void SVC_Handler_C(unsigned int * svc_args)
{
uint8_t svc_number;
svc_number = ((char *) svc_args[6])[-2]; // Memory[(Stacked PC)-2]
// marking kernel as busy
kernel_busy = 1;
switch(svc_number) {
//************* SVC( 0 ) OS Start
case (0): // OS start
// Starting the task scheduler
//TWP playing a trick here!? by making curr = next, will make next's stack and current's stack the same stack!
// will save (garbage) current register values, and then immediately restore them as next's initial values :-)
curr_task = rtr_q_h; // Switch to head ready-to-run task (Current task)
// when current task was put in RTRQ its state was set to RUNNING
svc_exc_return = HW32_REG(( curr_task->stack_p )); // Return to thread with PSP
__set_PSP(( (uint32_t) curr_task->stack_p + 10*4)); // Set PSP to @R0 of task 0 exception stack frame
NVIC_SetPriority(PendSV_IRQn, 0xFF); // Set PendSV to lowest possible priority
if (SysTick_Config(os_sysTickTicks) != 0) // 1000 Hz SysTick interrupt on 16MHz core clock
{
stop_cpu2;
// Impossible SysTick_Config number of ticks
}
__set_CONTROL(0x3); // Switch to use Process Stack, unprivileged state
__ISB(); // Execute ISB after changing CONTROL (architectural recommendation)
break;
//************* SVC( 1 ) Thread Yield
case (1): // Thread Yield
if (curr_task != rtr_q_h)
{
// Context switching needed
ScheduleContextSwitch();
}
__ISB();
break;
//************* SVC( 2 ) Stack Frame Allocation for First Launch
//TWPV6: no longer used! Functionality moved to osThreadCreate ... case left here (for now)
case (2): // Stack Allocation
__ISB();
break;
default:
#if ((ENABLE_KERNEL_PRINTF) && (ENABLE_KERNEL_PRINTF == 1))
printf("ERROR: Unknown SVC service number\n\r");
printf("- SVC number 0x%x\n\r", svc_number);
#endif
stop_cpu2;
break;
} // end switch
// marking kernel as normal
kernel_busy = 0;
}
void TCM_Disable(void)
{
__DSB();
__ISB();
SCB->ITCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk;
SCB->DTCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk;
__DSB();
__ISB();
}
uint32_t softdevice_handler_init(nrf_clock_lfclksrc_t clock_source,
void * p_ble_evt_buffer,
uint16_t ble_evt_buffer_size,
softdevice_evt_schedule_func_t evt_schedule_func)
{
uint32_t err_code;
// Save configuration.
#if defined (BLE_STACK_SUPPORT_REQD)
// Check that buffer is not NULL.
if (p_ble_evt_buffer == NULL)
{
return NRF_ERROR_INVALID_PARAM;
}
// Check that buffer is correctly aligned.
if (!is_word_aligned(p_ble_evt_buffer))
{
return NRF_ERROR_INVALID_PARAM;
}
mp_ble_evt_buffer = (uint8_t *)p_ble_evt_buffer;
m_ble_evt_buffer_size = ble_evt_buffer_size;
#else
// The variables p_ble_evt_buffer and ble_evt_buffer_size is not needed if BLE Stack support
// is not required.
UNUSED_PARAMETER(p_ble_evt_buffer);
UNUSED_PARAMETER(ble_evt_buffer_size);
#endif
m_evt_schedule_func = evt_schedule_func;
//Enabling FPU for SoftDevice
#ifdef S132
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
// Initialize SoftDevice.
err_code = sd_softdevice_enable(clock_source, softdevice_assertion_handler);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
#ifdef S132
SCB->CPACR = 0;
__DSB();
__ISB();
#endif
m_softdevice_enabled = true;
// Enable BLE event interrupt (interrupt priority has already been set by the stack).
return sd_nvic_EnableIRQ(SOFTDEVICE_EVT_IRQ);
}
void nrf_nvmc_write_word(uint32_t address, uint32_t value)
{
// Enable write.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
__ISB();
__DSB();
*(uint32_t*)address = value;
wait_for_flash_ready();
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
__ISB();
__DSB();
}
void nrf_nvmc_page_erase(uint32_t address)
{
// Enable erase.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
__ISB();
__DSB();
// Erase the page
NRF_NVMC->ERASEPAGE = address;
wait_for_flash_ready();
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
__ISB();
__DSB();
}
static void tt_use_PSP(unsigned int irq_stack_addr)
{
__set_PSP(__get_MSP());
__set_MSP(irq_stack_addr);
__set_CONTROL(2);
__ISB();
}
/**
* \brief Performs the low-level initialization of the chip.
*/
extern WEAK void LowLevelInit(void)
{
SystemInit();
#ifndef MPU_EXAMPLE_FEATURE
_SetupMemoryRegion();
#endif
#if defined(FFT_DEMO) && (defined(__GNUC__) || defined(__CC_ARM))
/* Enabling the FPU */
SCB->CPACR |= 0x00F00000;
__DSB();
__ISB();
#endif
#if defined(ENABLE_TCM) && defined(__GNUC__)
volatile char *dst = &_sitcm;
volatile char *src = &_itcm_lma;
/* copy code_TCM from flash to ITCM */
while (dst < &_eitcm)
*dst++ = *src++;
#endif
}
/**
* @brief Enters Sleep mode.
*
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
*
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
* systick interrupt when used as time base for Timeout
*
* @param Regulator Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @note This parameter is not used for the STM32F7 family and is kept as parameter
* just to maintain compatibility with the lower power families.
* @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Ensure that all instructions done before entering SLEEP mode */
__DSB();
__ISB();
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
int main(void)
{
int SYSm;
/* Initialise MPU, I/O and SysTick */
SCS_init();
UART_init();
SysTick_init();
/* Finally change Thread mode to unprivileged
* but continue using Main Stack Pointer */
SYSm = __MRS_control();
SYSm |= 1;
__MSR_control(SYSm);
/* Flush and refill pipline with unprivileged permissions */
__ISB();
printf("Cortex-M3 Example - Build 3\n");
/* Loop forever */
while( 1 )
{
Display_80((char*) ".");
}
}
// (re)initialize UART0 as a monitor output to 250000,n,8,1
static void TXBegin(void) {
// Disable UART interrupt in NVIC
NVIC_DisableIRQ( UART_IRQn );
// We NEED memory barriers to ensure Interrupts are actually disabled!
// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
__DSB();
__ISB();
// Disable clock
pmc_disable_periph_clk( ID_UART );
// Configure PMC
pmc_enable_periph_clk( ID_UART );
// Disable PDC channel
UART->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
// Reset and disable receiver and transmitter
UART->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
// Configure mode: 8bit, No parity, 1 bit stop
UART->UART_MR = UART_MR_CHMODE_NORMAL | US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO;
// Configure baudrate (asynchronous, no oversampling) to BAUDRATE bauds
UART->UART_BRGR = (SystemCoreClock / (BAUDRATE << 4));
// Enable receiver and transmitter
UART->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
}
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
__DSB();
__ISB();
}
int init_sys(void)
{
SCB->CCR |= SCB_CCR_STKALIGN_Msk; // enable double word stack alignment
PSP_array[0] = ((unsigned int)task0_stack) + (sizeof task0_stack) - 16*4; // top of stack
HW32_REG((PSP_array[0] + (14<<2))) = (unsigned long)task0; // initial Program Counter
HW32_REG((PSP_array[0] + (15<<2))) = 0x01000000; // initial PSR
PSP_array[1] = ((unsigned int)task1_stack) + (sizeof task1_stack) - 16*4;
HW32_REG((PSP_array[1] + (14<<2))) = (unsigned long)task1;
HW32_REG((PSP_array[1] + (15<<2))) = 0x01000000;
curr_task = 0;
__set_PSP((PSP_array[curr_task] + 16*4)); // set PSP to top of stack
NVIC_SetPriority(PendSV_IRQn, 0xFF);
SysTick_Config(168000);
__set_CONTROL(0x3);
__ISB();
task0();
/*while(1) {
stop_cpu;
}; */
}
/**
* @brief Claim one or more MPU subregions for a thread.
* @param num_regions The number of regions to claim.
*/
bool bitmap_heap_mpu_claim(heap_claim_t* claim)
{
bool rc=false;
/** Search each heap... */
for(heap_num=0; !rc && heap_num < heap_count; heap_num++)
{
if ( HEAP_STATE(heap_num)->heap_flags & CARIBOU_BITMAP_HEAP_MPU )
{
int subregion = locate_free_mpu_subregion();
if ( subregion >= 0 )
{
uint32_t subregion_bit = ((1<<subregion)<<MPU_RASR_SRD_Pos);
/* retrieve the MPU region number from the heap state */
int region = (HEAP_STATE(heap_num)->heap_flags & CARIBOU_BITMAP_HEAP_REGION_MSK);
claim->mpu_heap_num = heap_num;
claim->mpu_region = region;
claim->mpu_subregion = subregion;
/* Select the region for the thread */
MPU->RNR = claim->mpu_region+1;
/* Disable the higher (protection) level subregion mask, enabling access to the subregion */
MPU->RASR |= subregion_bit;
/* make a back-link to the thread indexed by subregion */
//HEAP_STATE(heap_num)->heap_thread[subregion] = thread;
/* Just mark it in use for now, the thread will get populated afterwards */
/* Data Barrier */
__DSB();
/* Instruction Barrier */
__ISB();
HEAP_STATE(heap_num)->heap_thread[subregion] = 0xFFFFFFFF;
rc = true;
}
}
}
return rc;
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_L1Cache_InvalidateDCacheAll(void) {
/* setup */
uint32_t orig = __get_SCTLR();
uint32_t value = 0x0815U;
L1C_EnableCaches();
L1C_CleanDCacheAll();
/* test cached value gets lost */
// WHEN a value is written
value = 0x4711U;
// ... and the cache is invalidated
L1C_InvalidateDCacheAll();
// ... and the cache is disabled
L1C_DisableCaches();
// THEN the new value has been lost
ASSERT_TRUE(value == 0x0815U);
/* tear down */
L1C_InvalidateDCacheAll();
__set_SCTLR(orig);
__ISB();
}
mp_uint_t sdcard_read_blocks(uint8_t *buff, uint32_t sector, uint32_t count)
{
HAL_SD_ErrorTypedef err;
// If buffer is unaligned or located in CCM don't use DMA.
if (CCM_BUFFER(buff) || UNALIGNED_BUFFER(buff)) {
if (UNALIGNED_BUFFER(buff)) {
printf("unaligned read buf:%p count%lu \n", buff, count);
}
// This transfer has to be done in an atomic section.
mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
err = HAL_SD_ReadBlocks(&SDHandle, (uint32_t*)buff,
sector * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE, count);
MICROPY_END_ATOMIC_SECTION(atomic_state);
} else {
// Disable USB IRQ to prevent FatFS/MSC contention
HAL_NVIC_DisableIRQ(OTG_FS_IRQn); __DSB(); __ISB();
dma_init(SDIO_TXRX_STREAM, SDIO_TXRX_CHANNEL, DMA_PERIPH_TO_MEMORY);
err = HAL_SD_ReadBlocks_DMA(&SDHandle, (uint32_t*)buff,
sector * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE, count);
if (err == SD_OK) {
err = HAL_SD_CheckReadOperation(&SDHandle, SDIO_TIMEOUT);
}
if (err != SD_OK) {
printf("read buf:%p addr:%lu count%lu error:%d\n", buff, sector, count, err);
}
dma_deinit();
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
}
return (err != SD_OK);
}
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit(void)
{
/* The Vector table base address is given by linker script. */
#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
#else
extern uint32_t __VECTOR_TABLE[];
#endif
/* Enable FPU */
#if ((1 == __FPU_PRESENT) && (1 == __FPU_USED))
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* M4 core clock root configuration. */
/* Initialize Cache */
/* Enable System Bus Cache */
/* set command to invalidate all ways and write GO bit
to initiate command */
LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
/* Wait until the command completes */
while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK);
/* Enable system bus cache, enable write buffer */
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
__ISB();
/* Enable Code Bus Cache */
/* set command to invalidate all ways and write GO bit
to initiate command */
LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK);
/* Enable code bus cache, enable write buffer */
LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
__ISB();
__DSB();
/* Relocate vector table */
#if defined(__CC_ARM)
SCB->VTOR = (uint32_t)Image$$VECTOR_ROM$$Base + VECT_TAB_OFFSET;
#else
SCB->VTOR = (uint32_t)__VECTOR_TABLE + VECT_TAB_OFFSET;
#endif
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
/* Switch back Thread mode to privileged */
__set_CONTROL(THREAD_MODE_PRIVILEGED | SP_PROCESS);
/* Execute ISB instruction to flush pipeline as recommended by Arm */
__ISB();
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
/* Switch back Thread mode to privileged */
__set_CONTROL(2);
/* Execute ISB instruction to flush pipeline as recommended by Arm */
__ISB();
}
void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
{
// Enable write.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
__ISB();
__DSB();
for (uint32_t i = 0; i < num_words; i++)
{
((uint32_t*)address)[i] = src[i];
wait_for_flash_ready();
}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
__ISB();
__DSB();
}
void myFMC_Erase(uint32_t u32addr)
{
outp32(FMC_ISPCMD, 0x22);
outp32(FMC_ISPADR, u32addr);
outp32(FMC_ISPTRG, 0x01);
__ISB();
}
/**
* @brief enable the MPU
*/
void arm_core_mpu_enable(void)
{
/* Enable MPU */
SYSMPU->CESR |= SYSMPU_CESR_VLD_MASK;
/* Make sure that all the registers are set before proceeding */
__DSB();
__ISB();
}
void myFMC_Write(uint32_t u32addr, uint32_t u32data)
{
outp32(FMC_ISPCMD, 0x21);
outp32(FMC_ISPADR, u32addr);
outp32(FMC_ISPDAT, u32data);
outp32(FMC_ISPTRG, 0x01);
__ISB();
}
inline void usbdbg_set_irq_enabled(bool enabled)
{
if (enabled) {
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
} else {
HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
}
__DSB(); __ISB();
}
