int board_late_init(void) { #ifdef CONFIG_S6E63D6 struct s6e63d6 data = { /* * See comment in mxc_spi.c::decode_cs() for .cs field format. * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect * 2 of the SPI controller #1, since it is unused. */ .cs = 2 | (57 << 8), .bus = 0, .id = 0, }; int ret; /* SPI1 */ mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); /* start SPI1 clock */ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); /* GPIO 57 */ /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); /* SPI1 CS2 is free */ ret = s6e63d6_init(&data); if (ret) return ret; /* * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC * OLED display connected to a S6E63D6 SPI display controller in the * 18 bit RGB mode */ s6e63d6_index(&data, 2); s6e63d6_param(&data, 0x0182); s6e63d6_index(&data, 3); s6e63d6_param(&data, 0x8130); s6e63d6_index(&data, 0x10); s6e63d6_param(&data, 0x0000); s6e63d6_index(&data, 5); s6e63d6_param(&data, 0x0001); s6e63d6_index(&data, 0x22); #endif return 0; } #endif int checkboard (void) { printf("Board: Phytec phyCore i.MX31\n"); return 0; }
void uart_init(void) { /*串口初始化,配置串口参数*/ struct s5pv210_gpio *gpio_base =(struct s5pv210_gpio *)S5PV210_GPIO_BASE; struct s5pv2xx_uart *uart_base =(struct s5pv2xx_uart *)S5PV210_UART_BASE; unsigned int var; /*配置功能引脚*/ var = readl(&gpio_base->a0.con); var &= ~(0xff<<0); var |= (0x22<<0); writel(var,&gpio_base->a0.con); /*配置串口控制器*/ __REG(&uart_base->ulcon) = 0x3; //配置ulcon实现 8位字长 1个停止位 无奇偶校验位 正常模式(非红外模式) __REG(&uart_base->ucon) = 0x5; //使能发送、接收 /*配置波特率*/ /* 计算方法:假设SCLK_UART为66.5MHZ,设定的波特率为115200 DIV_VAL =(SCLK_UART/(Baud_Rate*16))-1 =((66.5*1000000)/(115200*16))-1000000 =35.07855903 UBRDIVn 的值为整数位的值, UDIVSLOTn的值: 16*小数位 的结果的第一位的值说在表格中对应的值(表格看数据手册880页) 约为 16*0.07=1.12 第一位为1,1在表格对应为0x0080 UBRDIVn = 35 UDIVSLOTn = 0x0080 */ __REG(&uart_base->ubrdiv) = 35; __REG(&uart_base->udivslot) = 0x80; }
void SF_NvmodeWrite(void) { SF_PrechargeAll(); reg_SFCTL = CMD_LCR; /* Set to LCR mode */ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ }
void mxc_serial_putc(const char c) { __REG(UART_PHYS + UTXD) = c; while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) ; if(c == '\n') mxc_serial_putc('\r'); }
int board_init (void) { __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ __REG(CSCR_L(0)) = 0x10000d03; __REG(CSCR_A(0)) = 0x00720900; __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ __REG(CSCR_L(1)) = 0x444a4541; __REG(CSCR_A(1)) = 0x44443302; __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ __REG(CSCR_L(4)) = 0x22252521; __REG(CSCR_A(4)) = 0x22220a00; /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); /* setup pins for I2C2 (for EEPROM, RTC) */ mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); gd->bd->bi_arch_number = 447; /* board id for linux */ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ return 0; }
void imx_gpio_set_pin(unsigned int pin, int val) { u32 gpio_num = IOMUX_TO_GPIO(pin); u32 gpio_off = GPIO_TO_INDEX(gpio_num); u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num)); if (val) __REG(baddr + GPIO_DR) |= (1 << gpio_off); else __REG(baddr + GPIO_DR) &= ~(1 << gpio_off); }
void imx_gpio_pin_cfg_dir(unsigned int pin, int dir) { u32 gpio_num = IOMUX_TO_GPIO(pin); u32 gpio_off = GPIO_TO_INDEX(gpio_num); u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num)); if (dir) __REG(baddr + GPIO_GDIR) |= (1 << gpio_off); else __REG(baddr + GPIO_GDIR) &= ~(1 << gpio_off); }
void SF_NvmodeErase(void) { SF_PrechargeAll(); reg_SFCTL = CMD_LCR; /* Set to LCR mode */ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ while(!SF_Ready()); }
void serial_putc (const char c) { __REG(UART_PHYS + UTXD) = c; /* wait for transmitter to be ready */ while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); /* If \n, also do \r */ if (c == '\n') serial_putc ('\r'); }
/*! * This function enables/disables the general purpose function for a particular * signal. * * @param gp one signal as defined in \b #iomux_gp_func_t * @param en \b #true to enable; \b #false to disable */ void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) { u32 l; l = __REG(IOMUXGPR); if (en) l |= gp; else l &= ~gp; __REG(IOMUXGPR) = l; }
static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; __REG(UART_PHYS + UFCR) = (__REG(UART_PHYS + UFCR) & ~UFCR_RFDIV) | (4 << 7); /* divide input clock by 2 */ __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); }
void myputc(char c) { /* 发送一个字符 */ struct s5pv2xx_uart *uart_base =(struct s5pv2xx_uart *)S5PV210_UART_BASE; /* 判断发送缓冲区是否为空 */ while(!(__REG(&uart_base->utrstat)&(0x01<<2))); /*再在发送数据 */ __REG(&uart_base->utxh) = c; //设置要发送的值给串口缓冲区 }
void serial_setbrg (void) { u32 clk = mx31_get_ipg_clk(); if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); }
/* Get Status register */ u32 SF_SR(void) { u32 tmp,tmp1; reg_SFCTL = CMD_PROGRAM; tmp = __REG(CFG_FLASH_BASE); reg_SFCTL = CMD_NORMAL; reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); return tmp; }
int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ __REG(CSCR_U(5)) = 0x0000d843; __REG(CSCR_L(5)) = 0x22252521; __REG(CSCR_A(5)) = 0x22220a00; /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); mx31_spi2_hw_init(); return 0; }
void led_ctrl(u32 led_flag) { u32 led_reg, i; for( i=0; i<0x100000; i++ ); led_reg = 0x020b4004; if( LED_ON == led_flag ){ __REG(led_reg) = 0x0; } else { __REG(led_reg) = 0x3; } }
int board_init(void) { int i; #if 0 /* CS0: Nor Flash */ /* * These are values from the RedBoot sources by Freescale. However, * under U-Boot with this configuration 32-bit accesses don't work, * lower 16 bits of data are read twice for each 32-bit read. */ __REG(CSCR_U(0)) = 0x23524E80; __REG(CSCR_L(0)) = 0x10000D03; /* WRAP bit (1) is suspicious here, but * disabling it doesn't help either */ __REG(CSCR_A(0)) = 0x00720900; #endif /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); /* PBC setup */ /* Enable UART transceivers also reset the Ethernet/external UART */ readw(CS4_BASE + 4); writew(0x8023, CS4_BASE + 4); /* RedBoot also has an empty loop with 100000 iterations here - * clock doesn't run yet */ for (i = 0; i < 100000; i++) ; /* Clear the reset, toggle the LEDs */ writew(0xDF, CS4_BASE + 6); /* clock still doesn't run */ for (i = 0; i < 100000; i++) ; /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ readb(CS4_BASE + 8); readb(CS4_BASE + 7); readb(CS4_BASE + 8); readb(CS4_BASE + 7); gd->bd->bi_arch_number = 447; /* board id for linux */ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ return 0; }
void mx31_spi2_hw_init(void) { /* SPI2 */ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); /* start SPI2 clock */ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); }
static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) | (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF); __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); }
int board_early_init_f(void) { __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ __REG(CSCR_L(0)) = 0xa0330d01; __REG(CSCR_A(0)) = 0x00220800; __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ __REG(CSCR_L(4)) = 0x444a4541; __REG(CSCR_A(4)) = 0x44443302; /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); /* SPI2 */ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); /* start SPI2 clock */ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); return 0; }
/* Erase SyncFlash */ void SF_Erase(u32 RowAddress) { reg_SFCTL = CMD_NORMAL; __REG(RowAddress); reg_SFCTL = CMD_PREC; __REG(RowAddress); reg_SFCTL = CMD_LCR; /* Set LCR mode */ __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ while(!SF_Ready()); }
/* Issue the precharge all command */ void SF_PrechargeAll(void) { /* Set Precharge Command */ reg_SFCTL = CMD_PREC; /* Issue Precharge All Command */ __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); }
static void board_nand_setup(void) { /* CS3: NAND 8-bit */ static const struct mxc_weimcs cs3 = { /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) }; mxc_setup_weimcs(3, &cs3); __REG(IOMUXC_GPR) |= 1 << 13; mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO)); /* Make sure to reset the fpga else you cannot access NAND */ qong_fpga_reset(); /* Enable NAND flash */ gpio_set_value(15, 1); gpio_set_value(14, 1); gpio_direction_output(15, 0); gpio_direction_input(16); gpio_direction_input(14); }
/* Issue the precharge all command */ void SF_PrechargeAll(void) { u32 tmp; reg_SFCTL = CMD_PREC; /* Set Precharge Command */ tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ }
void kmain(void) { __REG(_P2V(UART_PHYS + UTXD)) = 'B'; __REG(UART_PHYS + UTXD) = 'A'; cprintf("Bless!!!! %d\n", 1000); cprintf("$$ Say hello in TrustZone ^^Normal^^ World!\n"); // transit to Secure Monitor (Dst: Secure World) asm volatile("smc #0\n\t"); cprintf("$$ Back from secure world!\n"); asm volatile("smc #0\n\t"); cprintf("Come back to life again!\n"); while(1); }
/* * Test whether a character is in the RX buffer */ int serial_tstc (void) { /* If receive fifo is empty, return false */ if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) return 0; return 1; }
static u32 __get_mcu_main_clk(void) { u32 reg, freq; reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >> MXC_CCM_CACRR_ARM_PODF_OFFSET; freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ); return freq / (reg + 1); }
static u32 __get_periph_clk(void) { u32 reg; reg = __REG(MXC_CCM_CBCDR); if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { reg = __REG(MXC_CCM_CBCMR); switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK) >> MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) { case 0: return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); case 1: case 2: return CONFIG_MX6_HCLK_FREQ; default: return 0; } } else {
int imx_gpio_get_pin(unsigned int pin) { u32 gpio_num = IOMUX_TO_GPIO(pin); u32 gpio_off = GPIO_TO_INDEX(gpio_num); u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num)); return (__REG(baddr + GPIO_DR) & (1 << gpio_off)) ? 1 : 0; }
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { int i; for(i = 0; i < cnt; i += 4) { SF_PrechargeAll(); reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ __REG(addr + i) = __REG((u32)src + i); while(!SF_Ready()); } SF_Normal(); return ERR_OK; }