static void gpio_init(void)
{
/*
* Initialize SDRAM pins
*/
#if CONFIG_NR_DRAM_BANKS == 2 /* Use Two Banks: DCS0 and DCS1 */
__gpio_as_sdram_x2_32bit();
#else
__gpio_as_sdram_32bit();
#endif
/*
* Initialize UART3 pins
*/
switch (CFG_UART_BASE) {
case UART0_BASE:
__gpio_as_uart0();
break;
case UART1_BASE:
__gpio_as_uart1();
break;
case UART2_BASE:
__gpio_as_uart2();
break;
case UART3_BASE:
__gpio_as_uart3();
break;
}
}
static void gpio_init(void)
{
/* board led pins */
__gpio_as_output(0);
__gpio_as_output(1);
__gpio_as_output(2);
__gpio_as_output(3);
__gpio_as_emc();
__gpio_as_uart0();
__gpio_as_uart1();
__gpio_as_uart2();
__gpio_as_uart3();
__gpio_as_scc();
__gpio_as_lcd_master();
__gpio_as_usb();
__gpio_as_eth();
__gpio_as_pwm();
__gpio_as_ps2();
__gpio_as_uprt();
__gpio_as_output(9); /* Mem R/B */
__gpio_as_output(10); /* M/CPU Select */
__gpio_as_output(13); /* LCDM Backlight */
__gpio_as_output(14); /* C/D Pin of LCDM */
__gpio_as_output(88); /* Beeper */
__gpio_as_output(89); /* Cash Box */
// __gpio_as_output(90); /* Modem Enable */
// __gpio_as_output(91); /* INTA_N, external RTC irq */
__harb_usb0_uhc(); /* USB port 0 as host */
// __harb_usb0_udc(); /* USB port 0 as device */
}
static void gpio_init(void)
{
__gpio_as_output(96); /* board led */
__gpio_as_output(104); /* cim */
__gpio_as_output(105); /* lcd module backlight */
__gpio_as_output(106); /* ac97 */
__gpio_as_output(107); /* uart */
__gpio_clear_pin(104); /* enable cim power */
__gpio_clear_pin(105); /* turn on lcd module backlight */
__gpio_set_pin(106); /* ac97 enable */
__gpio_set_pin(107); /* uart enable */
__gpio_as_uart0();
__gpio_as_uart1();
__gpio_as_uart2();
__gpio_as_uart3();
__gpio_as_emc();
__gpio_as_lcd_master();
__gpio_as_usb();
__gpio_as_ac97();
__gpio_as_cim();
__gpio_as_eth();
__harb_usb0_uhc(); /* USB port 0 as host port */
}
void init_gpio(void)
{
#if defined(CONFIG_JZ4760_CRATER)
//volatile int i=10000000;
/* set lcd function pin to low to avoid powering up lcd partially. */
__gpio_clear_lcd_24bit();
__gpio_as_output(GPIO_LCD_DISP_N);
__gpio_clear_pin(GPIO_LCD_DISP_N);
//while(i--);
//__gpio_as_output(GPIO_LCD_VCC_EN_N);
//__gpio_set_pin(GPIO_LCD_VCC_EN_N);
#endif
#if defined(CONFIG_JZ4760_Z800)
/*
* In z800 board PA30 is used as charge enable, we need to enable
* it before start system as a default.
*/
__gpio_clear_pin(32*0+27);
__gpio_as_output(32*0+27);
#endif
/* Init nand pins */
#if (CFG_NAND_BW8 == 1)
__gpio_as_nand_8bit(1);
#else
__gpio_as_nand_16bit(1);
#endif
/*Init lcd pins*/
#if defined(CONFIG_JZ4760_ANDROID_LCD_TRULY_TFT_ER61581)
__gpio_as_lcd_16bit();
#elif defined(CONFIG_JZ4760_ANDROID_LCD_YUE_TFT_YL10922NT)
__gpio_as_lcd_16bit();
#elif defined(CONFIG_JZ4760_PT701_8) || defined(CONFIG_JZ4760_PT701) || defined(CONFIG_JZ4760_TABLET_P2) || defined(CONFIG_JZ4760_LEPUS) || defined(CONFIG_JZ4760_PX7_2R) || defined(CONFIG_JZ4760_TABLET_8II)
__gpio_as_lcd_24bit();
#elif defined(CONFIG_JZ4760_ANDROID_LCD_PROBE)
__gpio_as_lcd_16bit();
#endif
/*
* Initialize UART1 pins
*/
#if CFG_UART_BASE == UART0_BASE
__gpio_as_uart0();
#elif CFG_UART_BASE == UART1_BASE
__gpio_as_uart1();
#elif CFG_UART_BASE == UART2_BASE
__gpio_as_uart2();
#else /* CFG_UART_BASE == UART1_BASE */
__gpio_as_uart3();
#endif
#if defined(CONFIG_JZ4760_PT701_8)
__gpio_clear_pin(GPIO_SPK_EN); // close speaker
#endif
}
static void gpio_init(void)
{
/*
* Initialize UART1 pins
*/
#if CFG_UART_BASE == UART0_BASE
__gpio_as_uart0();
#elif CFG_UART_BASE == UART1_BASE
__gpio_as_uart1();
#elif CFG_UART_BASE == UART2_BASE
__gpio_as_uart2();
#else /* CFG_UART_BASE == UART1_BASE */
__gpio_as_uart3();
#endif
}
static void gpio_init(void)
{
/*
* Initialize SDRAM pins
*/
#if CONFIG_NR_DRAM_BANKS == 2 /*Use Two Banks SDRAM*/
__gpio_as_sdram_x2_32bit();
#else
__gpio_as_sdram_32bit();
#endif
/*
* Initialize UART1 pins
*/
__gpio_as_uart1();
}
static void gpio_init(void)
{
/* board led pins */
__gpio_as_uart0();
__gpio_as_uart1();
__gpio_as_emc(0);
__gpio_as_dma();
__gpio_as_eth();
__gpio_as_pci();
__gpio_as_usbclk();
__gpio_as_output(67);
__gpio_as_output(68);
__gpio_as_output(69);
__gpio_as_output(70);
}
static void gpio_init(void)
{
/* For ethernet data line init */
__gpio_as_nand_16bit(1);
/*
* Initialize UART1 pins
*/
#if CFG_UART_BASE == UART0_BASE
__gpio_as_uart0();
#elif CFG_UART_BASE == UART1_BASE
__gpio_as_uart1();
#elif CFG_UART_BASE == UART2_BASE
__gpio_as_uart2();
#else /* CFG_UART_BASE == UART1_BASE */
__gpio_as_uart3();
#endif
}
static void gpio_init(void)
{
/* board led pins */
__gpio_as_output(96);
__gpio_as_output(97);
__gpio_as_output(98);
__gpio_as_output(99);
__gpio_as_uart0();
__gpio_as_uart1();
__gpio_as_uart2();
__gpio_as_uart3();
__gpio_as_emc();
__gpio_as_ssi();
__gpio_as_scc();
__gpio_as_msc();
__gpio_as_lcd_master();
__gpio_as_usb();
__gpio_as_ac97();
__gpio_as_eth();
__gpio_as_ps2();
}
/* NOTES:
* 1: Pins that are floated (NC) should be set as input and pull-enable.
* 2: Pins that are pull-up or pull-down by outside should be set as input
* and pull-disable.
* 3: Pins that are connected to a chip except sdram and nand flash
* should be set as input and pull-disable, too.
*/
static void jz_board_do_sleep(unsigned long *ptr)
{
unsigned char i;
/* Print messages of GPIO registers for debug */
for(i=0;i<GPIO_PORT_NUM;i++) {
dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
}
/* Save GPIO registers */
for(i = 1; i < GPIO_PORT_NUM; i++) {
*ptr++ = REG_GPIO_PXFUN(i);
*ptr++ = REG_GPIO_PXSEL(i);
*ptr++ = REG_GPIO_PXDIR(i);
*ptr++ = REG_GPIO_PXPE(i);
*ptr++ = REG_GPIO_PXIM(i);
*ptr++ = REG_GPIO_PXDAT(i);
*ptr++ = REG_GPIO_PXTRG(i);
}
/*
* Set all pins to pull-disable, and set all pins as input except
* sdram and the pins which can be used as CS1_N to CS4_N for chip select.
*/
__gpio_as_sleep();
/*
* Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
* Keep the pins' function used for chip select(CS) here according to your
* system to avoid chip select crashing with sdram when resuming from sleep mode.
*/
#if defined(CONFIG_JZ4750L_APUS)
/* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */
/* GPB26/CS2_N is connected to nand flash, needn't be changed. */
/* GPB28/CS3_N is used as cs8900's chip select, shouldn't be changed. */
/* GPB27/CS4_N is used as NOR's chip select, shouldn't be changed. */
#endif
/*
* Enable pull for NC pins here according to your system
*/
#if defined(CONFIG_JZ4750L_APUS)
#endif
/*
* If you must set some GPIOs as output to high level or low level,
* you can set them here, using:
* __gpio_as_output(n);
* __gpio_set_pin(n); or __gpio_clear_pin(n);
*/
#if defined(CONFIG_JZ4750L_APUS)
/* GPC7 which is used as AMPEN_N should be set to high to disable audio amplifier */
__gpio_as_output(32*2+7);
__gpio_set_pin(32*2+7);
#endif
#ifdef DEBUG
/* Keep uart function for printing debug message */
__gpio_as_uart0();
__gpio_as_uart1();
__gpio_as_uart2();
__gpio_as_uart3();
/* Print messages of GPIO registers for debug */
for(i=0;i<GPIO_PORT_NUM;i++) {
dprintk("sleep dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
}
#endif
}
