// USER CODE BEGIN (SRN22,1) void stm_src0(void) { pthread_t thread; pthread_running->lcx = __mfcr(PCXI); thread = pthread_running->next; // get next thread with same priority pthread_runnable_threads[thread->priority] = thread; pthread_running = thread; __dsync(); // required before PCXI manipulation (see RTOS porting guide) __mtcr(PCXI, thread->lcx); __asm("ji a11"); }
boolean IfxCpu_setCoreMode(Ifx_CPU *cpu, IfxCpu_CoreMode mode) { // this switch is only temporary required // once the IfxCan driver is generated via lldgen, we will vary the code without #ifdef #ifdef IFX_TC27x /* FIXME Copied from old TC27xA code, check that this is up to date code */ IfxCpu_CoreMode cpuMode; boolean RetVal; IfxScu_PMCSR_REQSLP modeSet; RetVal = TRUE; modeSet = IfxScu_PMCSR_REQSLP_Idle; /* Check the mode the CPU is in */ cpuMode = IfxCpu_getCoreMode(cpu); /* if requested mode is same as current mode nothing to do */ if (cpuMode != mode) { /* transition from halt to Run */ if (IfxCpu_CoreMode_halt == cpuMode) { if (IfxCpu_CoreMode_run == mode) { Ifx_CPU_DBGSR dbgsr; if (IfxCpu_getCoreId() != IfxCpu_getIndex(cpu)) { cpu->DBGSR.B.HALT = 0x2; } else { dbgsr.U = __mfcr(CPU_DBGSR); dbgsr.B.HALT = 0x2; __mtcr(CPU_DBGSR, dbgsr.U); } } else /* cannot go to any other mode e.g. IfxCpu_CoreMode_idle */ { RetVal = FALSE; } } /* From Run to Idle or vice versa */ else { if (IfxCpu_CoreMode_run == cpuMode) { if (IfxCpu_CoreMode_idle == mode) { modeSet = IfxScu_PMCSR_REQSLP_Idle; } else { RetVal = FALSE; } } /* idle to Run */ else if (IfxCpu_CoreMode_idle == cpuMode) { if (IfxCpu_CoreMode_run == mode) { modeSet = IfxScu_PMCSR_REQSLP_Run; } else { RetVal = FALSE; } } else { RetVal = FALSE; } if (TRUE == RetVal) { /* To take care of the Work Around in A step * In A Step the PMCSR is Cpu Endinit protected * in B step it is by safety endinit*/ uint16 password; uint32 wdtCon0_Val; Ifx_SCU_WDTCPU *watchdog; watchdog = &MODULE_SCU.WDTCPU[IfxCpu_getCoreId()]; /* FIXME access to the watchdog of an other CPU, this might not work! */ password = IfxScuWdt_getCpuWatchdogPassword(); IfxScuWdt_clearCpuEndinit(password); /* password access */ watchdog->CON0.U = (password << 2U) | 0x1U; /* modify access, E=0 */ watchdog->CON0.U = (password << 2U) | 0x2U; /* password access in advance */ watchdog->CON0.U = (password << 2U) | 0x1U; /* prepare write value */ wdtCon0_Val = ((0x0000U) << 16U) | (password << 2U) | (0x3U); MODULE_SCU.PMCSR[(uint32)IfxCpu_getIndex(cpu)].B.REQSLP = modeSet; /* modify access, E=1, reload WDT */ watchdog->CON0.U = wdtCon0_Val; IfxScuWdt_setCpuEndinit(password); } } } return RetVal; #else uint8 reqslp; boolean retValue; IfxCpu_ResourceCpu index = IfxCpu_getIndex(cpu); /*Modes such as HALT, SLEEP and STBY are not handled at CPU level */ retValue = ((mode == IfxCpu_CoreMode_halt) || (mode == IfxCpu_CoreMode_sleep) || (mode == IfxCpu_CoreMode_stby)) ? FALSE : TRUE; reqslp = (mode == IfxCpu_CoreMode_idle) ? IfxScu_PMCSR_REQSLP_Idle : IfxScu_PMCSR_REQSLP_Run; if (retValue == TRUE) { /*Check if the same core is requesting to change the core run mode */ if (IfxCpu_getCoreId() != index) { /*Request is for the other core */ /*To access PMCSR of other CPUs handle the safety EndInit protection */ uint16 safetyWdtPw = IfxScuWdt_getSafetyWatchdogPassword(); IfxScuWdt_clearSafetyEndinit(safetyWdtPw); MODULE_SCU.PMCSR[(uint32)IfxCpu_getIndex(cpu)].B.REQSLP = reqslp; IfxScuWdt_setSafetyEndinit(safetyWdtPw); cpu->DBGSR.B.HALT = 2; /*reset the HALT bit, if it is already done it is no harm in writing again */ } else { /*Request is for self, this request normally only for halt, otherwise the core is already running anyway! */ /*To access PMCSR of self handle the cpu EndInit protection */ uint16 cpuWdtPw = IfxScuWdt_getCpuWatchdogPassword(); IfxScuWdt_clearCpuEndinit(cpuWdtPw); MODULE_SCU.PMCSR[(uint32)index].B.REQSLP = reqslp; IfxScuWdt_setCpuEndinit(cpuWdtPw); } } return retValue; #endif }
void _start( void ) { /* Do a dsync before changing any of the csfr values, thus any previous * background state gets flushed first. Required for applications that jump * to the reset address. */ __dsync(); /* Set the PSW to its reset value in case of a warm start */ #if __USER_STACK __mtcr(PSW, 0x00000980); /* clear PSW.IS */ #else __mtcr(PSW, 0x00000b80); #endif /* Set the PCXS and PCXO to its reset value in case of a warm start */ unsigned int pcxi = __mfcr(PCXI); pcxi &= 0xfff00000; __mtcr(PCXI, pcxi); /* * Clear the ENDINIT bit in the WDT_CON0 register in order * to disable the write-protection for registers protected * via the EndInit feature (for example: WDT_CON1). */ _endinit_clear(); /* * Disable the Watchdog if requested. Watchdog is enabled by default. * The Watchdog is disabled after ENDINIT is set by _endinit_set(). */ #if __WATCHDOG_DISABLE WDT_CON1.U |= 0x8; _endinit_set(); _endinit_clear(); #endif /* * PMI_TC.003 workaround: * The TLB-A and TLB-B mappings are set to a page size of 16KB. */ #if __PMI_TC003_INITIAL__ && defined MMU_CON unsigned int mmu_con = __mfcr(MMU_CON); mmu_con &= 0xffffffe1; /* clear SZA and SZB */ mmu_con |= 0x00000014; /* set SZA=SZB=16k */ __mtcr(MMU_CON, mmu_con); #endif /* * Load Base Address of Trap Vector Table. * Disable this if not started from RESET vector. (E.g. * ROM monitors require to keep in control of vectors) */ #if __BTV_INIT __mtcr(BTV, (unsigned int)_lc_u_trap_tab); #endif /* * Load Base Address of Interrupt Vector Table. * Disable this if not started from RESET vector. (E.g. * ROM monitors require to keep in control of vectors) */ #if __BIV_INIT __mtcr(BIV, (unsigned int)(_lc_u_int_tab)); #endif /* * Load interupt stack pointer. * Disable this if not started from RESET vector. (E.g. * ROM monitors require to keep in control of vectors) */ #if __ISP_INIT unsigned int isp = (unsigned int)(_lc_ue_istack) & STACK_ALIGN; __mtcr(ISP, isp); #endif /* * PMU/PMI configuration. */ #if defined PMI_CON0 && defined __PMI_CON0_VALUE if(__PMI_CON0_INIT) PMI_CON0.U = __PMI_CON0_VALUE; #endif #if defined PMI_CON1 && defined __PMI_CON1_VALUE if(__PMI_CON1_INIT) PMI_CON1.U = __PMI_CON1_VALUE; #endif #if defined PMI_CON2 && defined __PMI_CON2_VALUE && \ ( defined _REGTC1337_H || defined _REGTC1367_H || defined _REGTC1387_H || defined _REGTC1728_H \ || defined _REGTC1746_H || defined _REGTC1747_H || defined _REGTC1768_H || defined _REGTC1782_H \ || defined _REGTC1784_H || defined _REGTC1184_H || defined _REGTC1797_H || defined _REGTC1197_H \ || defined _REGTC1734_H || defined _REGTC1767_H || defined _REGTC1736_H || defined _REGTC1732_H \ || defined _REGTC1738_H || defined _REGTC1167_H || defined _REGTC1735_H || defined _REGTC1724_H ) if(__PMI_CON2_INIT) PMI_CON2.U = __PMI_CON2_VALUE; #endif #if defined PMU_EIFCON && defined __PMU_EIFCON_VALUE if(__PMU_EIFCON_INIT) PMU_EIFCON.U = __PMU_EIFCON_VALUE; #endif /* * DMI configuration. */ #if defined DMI_CON && defined __DMI_CON_VALUE && \ ( defined _REGTC1167_H || defined _REGTC1197_H || defined _REGTC1337_H || defined _REGTC1367_H \ || defined _REGTC1387_H || defined _REGTC1728_H || defined _REGTC1734_H || defined _REGTC1738_H \ || defined _REGTC1746_H || defined _REGTC1747_H || defined _REGTC1767_H || defined _REGTC1768_H \ || defined _REGTC1782_H || defined _REGTC1784_H || defined _REGTC1184_H || defined _REGTC1797_H \ || defined _REGTC1724_H ) if(__DMI_CON_INIT) DMI_CON.U = __DMI_CON_VALUE; #endif /* * Data cache control (Reset 0H). * CPU_TC013 workaround: * The 16KB D-Cache is enabled to workaround * the CPU_TC013 functional problem. * NOTE: Setting the D-Cache size must be done at the * very beginning of the startup code. */ #if defined DMU_CON # if __CPU_TC013_INITIAL__ DMU_CON.U = 0x1; # endif #endif /* * Bus configuration EBU_CLC within endinit. */ # if defined EBU_CLC && defined __EBU_CLC_VALUE if(__EBU_CLC_INIT) EBU_CLC.U = __EBU_CLC_VALUE; # endif /* * Setting up the PLL after Reset. * * After reset, the system clock will be running at the VCO * base frequency devided by a factor KDIV. To set up the PLL * ater resert, next action must be executed. */ #if defined PLL_CLC && defined __PLL_CLC_VALUE #if __PLL_CLC_INIT #if ( defined _REGTC11IB_H ) #define __PLLBYP PLL1_BP #define __LOCK PLL1_LOCK if ( PLL_CLC.B.__PLLBYP == 0 ) { PLL_CLC.U = __PLL_CLC_VALUE; while( PLL_CLC.B.__LOCK==0); /* Wait until the PLL becomes locked */ } #else #define __PLL_CLC_SYSFS_VALUE ((__PLL_CLC_VALUE>>2)&0x1) #define __PLL_CLC_VCOBYP_VALUE ((__PLL_CLC_VALUE>>5)&0x1) #define __PLL_CLC_VCOSEL_VALUE ((__PLL_CLC_VALUE>>6)&0x3) #define __PLL_CLC_KDIV_VALUE ((__PLL_CLC_VALUE>>8)&0xf) #define __PLL_CLC_PDIV_VALUE ((__PLL_CLC_VALUE>>13)&0x3) #define __PLL_CLC_NDIV_VALUE ((__PLL_CLC_VALUE>>16)&0x7f) if ( PLL_CLC.B.BYPPIN == 0 ) { #if ( defined _REGTC1100_H || defined _REGTC1115_H || defined _REGTC1130_H ) while (OSC_CON.B.OSCR==1); /* Wait until the oscillator is running */ #else while (OSC_CON.B.OSCR==0); /* Wait until the oscillator is running */ #endif PLL_CLC.B.VCOBYP = 1; /* Enabled the VCO Bypass Mode */ PLL_CLC.B.VCOSEL = __PLL_CLC_VCOSEL_VALUE; /* Select the VCO band */ PLL_CLC.B.PDIV = __PLL_CLC_PDIV_VALUE; PLL_CLC.B.KDIV = __PLL_CLC_KDIV_VALUE; PLL_CLC.B.NDIV = __PLL_CLC_NDIV_VALUE; #if __PLL_CLC_VCOBYP_VALUE==0 PLL_CLC.B.OSCDISC = 0; /* Connect the oscillator to the PLL */ while( PLL_CLC.B.LOCK==0); /* Wait until the PLL becomes locked */ PLL_CLC.B.VCOBYP = 0; /* Disabled the VCO Bypass Mode */ #endif } #if ( defined _REGTC1100_H || defined _REGTC1115_H || defined _REGTC1130_H ) PLL_CLC.B.SYSFSL = __PLL_CLC_SYSFS_VALUE; /* System frequency select */ #else #if ( defined _REGTC1762_H || defined _REGTC1764_H || defined _REGTC1766B_H || defined _REGTC1161_H \ || defined _REGTC1162_H || defined _REGTC1163_H || defined _REGTC1164_H || defined _REGTC1165_H \ || defined _REGTC1166_H ) PLL_CLC.B.RSV = __PLL_CLC_SYSFS_VALUE; /* System frequency select */ #else PLL_CLC.B.SYSFS = __PLL_CLC_SYSFS_VALUE; /* System frequency select */ #endif #endif #endif #endif #endif /* * System Oscillator configuration */ #if defined SCU_OSCCON && defined __SCU_OSCCON_VALUE #if __SCU_OSCCON_INIT SCU_OSCCON.U=__SCU_OSCCON_VALUE; while(SCU_OSCCON.B.PLLLV==0); /* Oscillator not too low */ while(SCU_OSCCON.B.PLLHV==0); /* Oscillator not too high */ #endif #endif /* * Configure PLL Prescaler Mode. */ #if defined SCU_PLLCON1 && defined __SCU_PLLCON1_VALUE #if __SCU_PLLCON1_INIT #define __SCU_PLLCON1__K1DIV_VALUE ((__SCU_PLLCON1_VALUE>>16)&0x3f) SCU_PLLCON1.B.K1DIV=__SCU_PLLCON1__K1DIV_VALUE; while(SCU_PLLSTAT.B.K1RDY==0); /* Wait until K1-Divider is ready to operate */ #endif #endif #if defined SCU_PLLCON0 && defined __SCU_PLLCON0_VALUE #if __SCU_PLLCON0_INIT SCU_PLLCON0.B.VCOBYP=1; /* Enabled the VCO Bypass Mode */ while(SCU_PLLSTAT.B.VCOBYST==0); /* Wait until prescaler mode is entered */ #define __SCU_PLLCON0__VCOPWD_VALUE ((__SCU_PLLCON0_VALUE>>1)&0x1) #define __SCU_PLLCON0__NDIV_VALUE ((__SCU_PLLCON0_VALUE>>9)&0x7f) #define __SCU_PLLCON0__PDIV_VALUE ((__SCU_PLLCON0_VALUE>>24)&0xf) SCU_PLLCON0.B.PDIV=__SCU_PLLCON0__PDIV_VALUE; SCU_PLLCON0.B.NDIV=__SCU_PLLCON0__NDIV_VALUE; SCU_PLLCON0.B.VCOPWD=__SCU_PLLCON0__VCOPWD_VALUE; /* power down VCO */ #if __SCU_PLLCON0__VCOPWD_VALUE==0 /* * Configure PLL normal mode. */ SCU_PLLCON0.B.CLRFINDIS=1; /* Connect VCO to the oscillator */ while(SCU_PLLSTAT.B.FINDIS==1); /* Wait until oscillator is connected to the VCO */ SCU_PLLCON0.B.RESLD=1; /* Restart VCO lock detection */ while(SCU_PLLSTAT.B.VCOLOCK==0); /* Wait until the VCO becomes locked */ SCU_PLLCON0.B.VCOBYP=0; /* Disable the VCO Bypass Mode */ while(SCU_PLLSTAT.B.VCOBYST==1); /* Wait until normal mode is entered */ #endif #endif #endif #if defined SCU_PLLCON1 && defined __SCU_PLLCON1_VALUE #if __SCU_PLLCON1_INIT #define __SCU_PLLCON1__K2DIV_VALUE ((__SCU_PLLCON1_VALUE>>0)&0x3f) SCU_PLLCON1.B.K2DIV=__SCU_PLLCON1__K2DIV_VALUE; #endif #endif /* * Configure system clock register. */ #if defined STM_CLC && defined __STM_CLC_VALUE if(__STM_CLC_INIT) STM_CLC.U = __STM_CLC_VALUE; #endif /* * Set the ENDINIT bit in the WDT_CON0 register again * to enable the write-protection and to prevent a time-out. */ _endinit_set(); /* * Initialize Bus configuration registers: * Set register-values according to define's created by the GUI * * The recommended sequence of setting registers is as follows: * 1.EBUCON * 2.All other EBU registers except SDRAM specific registers * 3.SDRMCON0 * 4.SDRMMOD0 * 5.SDRMREF0 * 6.SDRMCON1 * 7.SDRMMOD1 * 8.SDRMREF1 */ #if defined EBU_CON && defined __EBU_CON_VALUE if(__EBU_CON_INIT) EBU_CON.U = __EBU_CON_VALUE; #endif #if defined EBU_ADDRSEL0 && defined __EBU_ADDRSEL0_VALUE if(__EBU_ADDRSEL0_INIT) EBU_ADDRSEL0.U = __EBU_ADDRSEL0_VALUE; #endif #if defined EBU_ADDRSEL1 && defined __EBU_ADDRSEL1_VALUE if(__EBU_ADDRSEL1_INIT) EBU_ADDRSEL1.U = __EBU_ADDRSEL1_VALUE; #endif #if defined EBU_ADDRSEL2 && defined __EBU_ADDRSEL2_VALUE if(__EBU_ADDRSEL2_INIT) EBU_ADDRSEL2.U = __EBU_ADDRSEL2_VALUE; #endif #if defined EBU_ADDRSEL3 && defined __EBU_ADDRSEL3_VALUE if(__EBU_ADDRSEL3_INIT) EBU_ADDRSEL3.U = __EBU_ADDRSEL3_VALUE; #endif #if defined EBU_ADDRSEL4 && defined __EBU_ADDRSEL4_VALUE if(__EBU_ADDRSEL4_INIT) EBU_ADDRSEL4.U = __EBU_ADDRSEL4_VALUE; #endif #if defined EBU_ADDRSEL5 && defined __EBU_ADDRSEL5_VALUE if(__EBU_ADDRSEL5_INIT) EBU_ADDRSEL5.U = __EBU_ADDRSEL5_VALUE; #endif #if defined EBU_ADDRSEL6 && defined __EBU_ADDRSEL6_VALUE if(__EBU_ADDRSEL6_INIT) EBU_ADDRSEL6.U = __EBU_ADDRSEL6_VALUE; #endif #if defined EBU_BFCON && defined __EBU_BFCON_VALUE if(__EBU_BFCON_INIT) EBU_BFCON.U = __EBU_BFCON_VALUE; #endif #if defined EBU_BUSAP0 && defined __EBU_BUSAP0_VALUE if(__EBU_BUSAP0_INIT) EBU_BUSAP0.U = __EBU_BUSAP0_VALUE; #endif #if defined EBU_BUSAP1 && defined __EBU_BUSAP1_VALUE if(__EBU_BUSAP1_INIT) EBU_BUSAP1.U = __EBU_BUSAP1_VALUE; #endif #if defined EBU_BUSAP2 && defined __EBU_BUSAP2_VALUE if(__EBU_BUSAP2_INIT) EBU_BUSAP2.U = __EBU_BUSAP2_VALUE; #endif #if defined EBU_BUSAP3 && defined __EBU_BUSAP3_VALUE if(__EBU_BUSAP3_INIT) EBU_BUSAP3.U = __EBU_BUSAP3_VALUE; #endif #if defined EBU_BUSAP4 && defined __EBU_BUSAP4_VALUE if(__EBU_BUSAP4_INIT) EBU_BUSAP4.U = __EBU_BUSAP4_VALUE; #endif #if defined EBU_BUSAP5 && defined __EBU_BUSAP5_VALUE if(__EBU_BUSAP5_INIT) EBU_BUSAP5.U = __EBU_BUSAP5_VALUE; #endif #if defined EBU_BUSAP6 && defined __EBU_BUSAP6_VALUE if(__EBU_BUSAP6_INIT) EBU_BUSAP6.U = __EBU_BUSAP6_VALUE; #endif #if defined EBU_BUSCON0 && defined __EBU_BUSCON0_VALUE if(__EBU_BUSCON0_INIT) EBU_BUSCON0.U = __EBU_BUSCON0_VALUE; #endif #if defined EBU_BUSCON1 && defined __EBU_BUSCON1_VALUE if(__EBU_BUSCON1_INIT) EBU_BUSCON1.U = __EBU_BUSCON1_VALUE; #endif #if defined EBU_BUSCON2 && defined __EBU_BUSCON2_VALUE if(__EBU_BUSCON2_INIT) EBU_BUSCON2.U = __EBU_BUSCON2_VALUE; #endif #if defined EBU_BUSCON3 && defined __EBU_BUSCON3_VALUE if(__EBU_BUSCON3_INIT) EBU_BUSCON3.U = __EBU_BUSCON3_VALUE; #endif #if defined EBU_BUSCON4 && defined __EBU_BUSCON4_VALUE if(__EBU_BUSCON4_INIT) EBU_BUSCON4.U = __EBU_BUSCON4_VALUE; #endif #if defined EBU_BUSCON5 && defined __EBU_BUSCON5_VALUE if(__EBU_BUSCON5_INIT) EBU_BUSCON5.U = __EBU_BUSCON5_VALUE; #endif #if defined EBU_BUSCON6 && defined __EBU_BUSCON6_VALUE if(__EBU_BUSCON6_INIT) EBU_BUSCON6.U = __EBU_BUSCON6_VALUE; #endif #if defined EBU_EMUAS && defined __EBU_EMUAS_VALUE if(__EBU_EMUAS_INIT) EBU_EMUAS.U = __EBU_EMUAS_VALUE; #endif #if defined EBU_EMUBAP && defined __EBU_EMUBAP_VALUE if(__EBU_EMUBAP_INIT) EBU_EMUBAP.U = __EBU_EMUBAP_VALUE; #endif #if defined EBU_EMUBC && defined __EBU_EMUBC_VALUE if(__EBU_EMUBC_INIT) EBU_EMUBC.U = __EBU_EMUBC_VALUE; #endif #if defined EBU_EMUCON && defined __EBU_EMUCON_VALUE if(__EBU_EMUCON_INIT) EBU_EMUCON.U = __EBU_EMUCON_VALUE; #endif #if defined EBU_EMUOVL && defined __EBU_EMUOVL_VALUE if(__EBU_EMUOVL_INIT) EBU_EMUOVL.U = __EBU_EMUOVL_VALUE; #endif #if defined EBU_SDRMCON0 && defined __EBU_SDRMCON0_VALUE if(__EBU_SDRMCON0_INIT) EBU_SDRMCON0.U = __EBU_SDRMCON0_VALUE; #endif #if defined EBU_SDRMOD0 && defined __EBU_SDRMOD0_VALUE if(__EBU_SDRMOD0_INIT) EBU_SDRMOD0.U = __EBU_SDRMOD0_VALUE; #endif #if defined EBU_SDRMREF0 && defined __EBU_SDRMREF0_VALUE if(__EBU_SDRMREF0_INIT) EBU_SDRMREF0.U = __EBU_SDRMREF0_VALUE; #endif #if defined EBU_SDRMCON1 && defined __EBU_SDRMCON1_VALUE if(__EBU_SDRMCON1_INIT) EBU_SDRMCON1.U = __EBU_SDRMCON1_VALUE; #endif #if defined EBU_SDRMOD1 && defined __EBU_SDRMOD1_VALUE if(__EBU_SDRMOD1_INIT) EBU_SDRMOD1.U = __EBU_SDRMOD1_VALUE; #endif #if defined EBU_SDRMREF1 && defined __EBU_SDRMREF1_VALUE if(__EBU_SDRMREF1_INIT) EBU_SDRMREF1.U = __EBU_SDRMREF1_VALUE; #endif #if defined CBS_MCDBBS && defined __CBS_MCDBBS_VALUE if(__CBS_MCDBBS_INIT) CBS_MCDBBS .U = __CBS_MCDBBS_VALUE; #endif #if defined SBCU_CON && defined __SBCU_CON_VALUE if(__SBCU_CON_INIT) SBCU_CON.U = __SBCU_CON_VALUE; #endif #if defined EBU_BUSRAP1 && defined __EBU_BUSRAP1_VALUE if(__EBU_BUSRAP1_INIT) EBU_BUSRAP1.U = __EBU_BUSRAP1_VALUE; #endif #if defined EBU_BUSRAP0 && defined __EBU_BUSRAP0_VALUE if(__EBU_BUSRAP0_INIT) EBU_BUSRAP0.U = __EBU_BUSRAP0_VALUE; #endif #if defined EBU_BUSRAP2 && defined __EBU_BUSRAP2_VALUE if(__EBU_BUSRAP2_INIT) EBU_BUSRAP2.U = __EBU_BUSRAP2_VALUE; #endif #if defined EBU_BUSRAP3 && defined __EBU_BUSRAP3_VALUE if(__EBU_BUSRAP3_INIT) EBU_BUSRAP3.U = __EBU_BUSRAP3_VALUE; #endif #if defined EBU_BUSRCON0 && defined __EBU_BUSRCON0_VALUE if(__EBU_BUSRCON0_INIT) EBU_BUSRCON0.U = __EBU_BUSRCON0_VALUE; #endif #if defined EBU_BUSRCON1 && defined __EBU_BUSRCON1_VALUE if(__EBU_BUSRCON1_INIT) EBU_BUSRCON1.U = __EBU_BUSRCON1_VALUE; #endif #if defined EBU_BUSRCON2 && defined __EBU_BUSRCON2_VALUE if(__EBU_BUSRCON2_INIT) EBU_BUSRCON2.U = __EBU_BUSRCON2_VALUE; #endif #if defined EBU_BUSRCON3 && defined __EBU_BUSRCON3_VALUE if(__EBU_BUSRCON3_INIT) EBU_BUSRCON3.U = __EBU_BUSRCON3_VALUE; #endif #if defined EBU_BUSWAP0 && defined __EBU_BUSWAP0_VALUE if(__EBU_BUSWAP0_INIT) EBU_BUSWAP0.U = __EBU_BUSWAP0_VALUE; #endif #if defined EBU_BUSWAP1 && defined __EBU_BUSWAP1_VALUE if(__EBU_BUSWAP1_INIT) EBU_BUSWAP1.U = __EBU_BUSWAP1_VALUE; #endif #if defined EBU_BUSWAP2 && defined __EBU_BUSWAP2_VALUE if(__EBU_BUSWAP2_INIT) EBU_BUSWAP2.U = __EBU_BUSWAP2_VALUE; #endif #if defined EBU_BUSWAP3 && defined __EBU_BUSWAP3_VALUE if(__EBU_BUSWAP3_INIT) EBU_BUSWAP3.U = __EBU_BUSWAP3_VALUE; #endif #if defined EBU_BUSWCON0 && defined __EBU_BUSWCON0_VALUE if(__EBU_BUSWCON0_INIT) EBU_BUSWCON0.U = __EBU_BUSWCON0_VALUE; #endif #if defined EBU_BUSWCON1 && defined __EBU_BUSWCON1_VALUE if(__EBU_BUSWCON1_INIT) EBU_BUSWCON1.U = __EBU_BUSWCON1_VALUE; #endif #if defined EBU_BUSWCON2 && defined __EBU_BUSWCON2_VALUE if(__EBU_BUSWCON2_INIT) EBU_BUSWCON2.U = __EBU_BUSWCON2_VALUE; #endif #if defined EBU_BUSWCON3 && defined __EBU_BUSWCON3_VALUE if(__EBU_BUSWCON3_INIT) EBU_BUSWCON3.U = __EBU_BUSWCON3_VALUE; #endif #if defined EBU_EXTBOOT && defined __EBU_EXTBOOT_VALUE if(__EBU_EXTBOOT_INIT) EBU_EXTBOOT.U = __EBU_EXTBOOT_VALUE; #endif #if defined EBU_MODCON && defined __EBU_MODCON_VALUE if(__EBU_MODCON_INIT) EBU_MODCON.U = __EBU_MODCON_VALUE; #endif #if defined EBU_DDRNCON && defined __EBU_DDRNCON_VALUE if(__EBU_DDRNCON_INIT) EBU_DDRNCON.U = __EBU_DDRNCON_VALUE; #endif #if defined EBU_DDRNMOD && defined __EBU_DDRNMOD_VALUE if(__EBU_DDRNMOD_INIT) EBU_DDRNMOD.U = __EBU_DDRNMOD_VALUE; #endif #if defined EBU_DDRNMOD2 && defined __EBU_DDRNMOD2_VALUE if(__EBU_DDRNMOD2_INIT) EBU_DDRNMOD2.U = __EBU_DDRNMOD2_VALUE; #endif #if defined EBU_DDRNPRLD && defined __EBU_DDRNPRLD_VALUE if(__EBU_DDRNPRLD_INIT) EBU_DDRNPRLD.U = __EBU_DDRNPRLD_VALUE; #endif #if defined EBU_DDRNTAG0 && defined __EBU_DDRNTAG0_VALUE if(__EBU_DDRNTAG0_INIT) EBU_DDRNTAG0.U = __EBU_DDRNTAG0_VALUE; #endif #if defined EBU_DDRNTAG1 && defined __EBU_DDRNTAG1_VALUE if(__EBU_DDRNTAG1_INIT) EBU_DDRNTAG1.U = __EBU_DDRNTAG1_VALUE; #endif #if defined EBU_DDRNTAG2 && defined __EBU_DDRNTAG2_VALUE if(__EBU_DDRNTAG2_INIT) EBU_DDRNTAG2.U = __EBU_DDRNTAG2_VALUE; #endif #if defined EBU_DDRNTAG3 && defined __EBU_DDRNTAG3_VALUE if(__EBU_DDRNTAG3_INIT) EBU_DDRNTAG3.U = __EBU_DDRNTAG3_VALUE; #endif #if defined EBU_DLLCON && defined __EBU_DLLCON_VALUE if(__EBU_DLLCON_INIT) EBU_DLLCON.U = __EBU_DLLCON_VALUE; #endif #if defined EBU_SDRMCON && defined __EBU_SDRMCON_VALUE if(__EBU_SDRMCON_INIT) EBU_SDRMCON.U = __EBU_SDRMCON_VALUE; #endif #if defined EBU_SDRMOD && defined __EBU_SDRMOD_VALUE if(__EBU_SDRMOD_INIT) EBU_SDRMOD.U = __EBU_SDRMOD_VALUE; #endif #if defined EBU_SDRMREF && defined __EBU_SDRMREF_VALUE if(__EBU_SDRMREF_INIT) EBU_SDRMREF.U = __EBU_SDRMREF_VALUE; #endif #if defined EBU_SDRSTAT && defined __EBU_SDRSTAT_VALUE if(__EBU_SDRSTAT_INIT) EBU_SDRSTAT.U = __EBU_SDRSTAT_VALUE; #endif /* * Inititialize global address registers a0/a1 to support * __a0/__a1 storage qualifiers of the C compiler. */ #if __A0A1_INIT void * a0 = _SMALL_DATA_; __asm( "mov.aa\ta0,%0"::"a"(a0) ); void * a1 = _LITERAL_DATA_; __asm( "mov.aa\ta1,%0"::"a"(a1) ); #endif /* * Inititialize global address registers a8/a9 to support * __a8/__a9 storage qualifiers of the C compiler. A8 and A9 * are reserved for OS use, or for application use in cases * where the application ans OS are tightly coupled. */ #if __A8A9_INIT void * a8 = _A8_DATA_; __asm( "mov.aa\ta8,%0"::"a"(a8) ); void * a9 = _A9_DATA_; __asm( "mov.aa\ta9,%0"::"a"(a9) ); #endif /* Setup the context save area linked list. */ #if __CSA_INIT // Still To be Done // - these pointer arrays csa_area_begin/end should be placed in memory, not on the stack // the simulator, however, will generate an error if 'static' is placed in front of the declarations # if !__CPU_TC051_INITIAL__ # define MAX_NR_OF_CSA_AREAS 1 extern int _lc_ub_csa_01[]; /* context save area 1 begin */ extern int _lc_ue_csa_01[]; /* context save area 1 end */ int * csa_area_begin[] = { _lc_ub_csa_01 }; int * csa_area_end[] = { _lc_ue_csa_01 }; # else # define MAX_NR_OF_CSA_AREAS 3 extern int _lc_ub_csa_01[]; /* context save area 1 begin */ extern int _lc_ue_csa_01[]; /* context save area 1 end */ extern int _lc_ub_csa_02[]; /* context save area 2 begin */ extern int _lc_ue_csa_02[]; /* context save area 2 end */ extern int _lc_ub_csa_03[]; /* context save area 3 begin */ extern int _lc_ue_csa_03[]; /* context save area 3 end */ int * csa_area_begin[] = { _lc_ub_csa_01, _lc_ub_csa_02, _lc_ub_csa_03 }; int * csa_area_end[] = { _lc_ue_csa_01, _lc_ue_csa_02, _lc_ue_csa_03 }; # endif int i, k; int no_of_csas; int * csa; unsigned int seg_nr, seg_idx, pcxi_val=0; _Bool first=true; for (i=0; i < MAX_NR_OF_CSA_AREAS; i++) { /* first calculate nr of CSAs in this area */ no_of_csas = (csa_area_end[i] - csa_area_begin[i]) >> 4; for (k=0; k < no_of_csas; k++) { csa = csa_area_begin[i] + k*16; /* Store null pointer in last CSA (= very first time!) */ *csa = pcxi_val; seg_nr = __extru( (int) csa, 28, 4) << 16; seg_idx = __extru( (int) csa, 6, 16); pcxi_val = seg_nr | seg_idx; if (first) { first = false; __mtcr(LCX, pcxi_val); } } __mtcr(FCX, pcxi_val); } #endif /* * PMU_TC.004 workaround: * The split mode is disabled on the LMB bus to workaround. */ #if __PMU_TC004_INITIAL__ && defined LFI_CON LFI_CON.U &= 0xfffffffe; #endif /* * Initialize and clear C variables. */ #if __C_INIT _c_init(); /* initialize data */ #endif /* * initialize __clocks_per_sec, * the oscillator frequency is defined by __fOSC. */ #if __CLOCKS_PER_SEC_INIT setclockpersec(); #endif /* initialize profiling if required */ #if __PROF_ENABLE__ __prof_init(); #endif /* * Call a user function within one can initialize the * registers protected via the EndInit feature. * Beware that protected registers are unlocked * for the duration of the Time-out Period only! */ #ifdef _CALL_ENDINIT _endinit_clear(); /* disable the write-protection */ _endinit(); _endinit_set(); /* enable the write-protection */ #endif /* * Call a user function before starting main(). */ #if defined __CALL_INIT _call_init(); #endif /* * Call C main program. */ #if __USE_ARGC_ARGV exit( main( _argcv( argcv, __ARGCV_BUFSIZE ), (char **)argcv ) ); #else exit( main( 0, NULL ) ); /* argc is 0 */ #endif /* * Default trap vectors are resolved from the C-library. */ #if __BTV_INIT # if __RESOLVE_TRAP_0 # pragma extern _trapmmu # endif # if __RESOLVE_TRAP_1 # pragma extern _trapprotection # endif # if __RESOLVE_TRAP_2 # pragma extern _trapinstruction # endif # if __RESOLVE_TRAP_3 # pragma extern _trapcontext # endif # if __RESOLVE_TRAP_4 # pragma extern _trapbus # endif # if __RESOLVE_TRAP_5 # pragma extern _trapassertion # endif # if __RESOLVE_TRAP_6 # pragma extern _trapsystem # endif # if __RESOLVE_TRAP_7 # pragma extern _trapnmi # endif #endif }
/********************************************************************************* * _start() - startup code *********************************************************************************/ void _Core0_start(void) { uint32 pcxi; uint16 cpuWdtPassword = IfxScuWdt_getCpuWatchdogPasswordInline(&MODULE_SCU.WDTCPU[0]); IFX_CFG_CPU_CSTART_PRE_C_INIT_HOOK(0); /*Test Stack, CSA and Cache */ /* Load user stack pointer */ __setareg(sp, __USTACK(0)); __dsync(); /* Set the PSW to its reset value in case of a warm start,clear PSW.IS */ __mtcr(CPU_PSW, IFXCSTART0_PSW_DEFAULT); /* Set the PCXS and PCXO to its reset value in case of a warm start */ pcxi = __mfcr(CPU_PCXI); pcxi &= IFXCSTART0_PCX_O_S_DEFAULT; /*0xfff00000; */ __mtcr(CPU_PCXI, pcxi); /*enable/disable program cache depending on the configuration */ IfxCpu_setProgramCache(IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE); /*enable/disable data cache depending on the configuration */ IfxCpu_setDataCache(IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE); /* Clear the ENDINIT bit in the WDT_CON0 register, inline funtion */ IfxScuWdt_clearCpuEndinitInline(&MODULE_SCU.WDTCPU[0], cpuWdtPassword); /* Load Base Address of Trap Vector Table. */ __mtcr(CPU_BTV, (uint32)__TRAPTAB(0)); /* Load Base Address of Interrupt Vector Table. we will do this later in the program */ __mtcr(CPU_BIV, (uint32)__INTTAB(0)); /* Load interupt stack pointer. */ __mtcr(CPU_ISP, (uint32)__ISTACK(0)); IfxScuWdt_setCpuEndinitInline(&MODULE_SCU.WDTCPU[0], cpuWdtPassword); /* initialize SDA base pointers */ __setareg(a0, __SDATA1(0)); __setareg(a1, __SDATA2(0)); /* These to be un commented if A8 and A9 are required to be initialized */ __setareg(a8, __SDATA3(0)); __setareg(a9, __SDATA4(0)); /* Setup the context save area linked list. */ IfxCpu_initCSA((uint32 *)__CSA(0), (uint32 *)__CSA_END(0)); /*Initialize the context save area for CPU0 */ { /*CPU and safety watchdogs are enabled by default, C initialization functions are not servicing the watchdogs */ uint16 safetyWdtPassword = IfxScuWdt_getSafetyWatchdogPassword(); IfxScuWdt_disableCpuWatchdog(cpuWdtPassword); IfxScuWdt_disableSafetyWatchdog(safetyWdtPassword); Ifx_C_Init(); /*Initialization of C runtime variables */ IfxScuWdt_enableCpuWatchdog(cpuWdtPassword); IfxScuWdt_enableSafetyWatchdog(safetyWdtPassword); } /*Initialize the clock system */ IFXCPU_CSTART_CCU_INIT_HOOK(); /*Call main function of Cpu0 */ __non_return_call(core0_main); }
void EcuM_AL_DriverInitOne(const EcuM_ConfigType* configPtr) { /* provide a proper clock */ Mcu_Init(configPtr->bsw_driver.init_one.mcu_cfg); Mcu_InitClock(0); Mcu_DistributePllClock(); /* ----------------------------------------------------------------------- Interrupt System: ----------------------------------------------------------------------- - four arbitration cycles (max. 255 interrupt sources) - two clocks per arbitration cycle */ __mtcr(0xFE2C, 0x00000000); /* load CPU interrupt control register */ __isync(); /* ----------------------------------------------------------------------- Peripheral Control Processor (PCP): ----------------------------------------------------------------------- - the PCP internal clock is always running - use Full Context save area (R[0] - R[7]) - start progam counter as left by last invocation - channel watchdog is disabled - maximum channel number checking is disabled */ /* - four arbitration cycles (max. 255 PCP channels) */ /* - two clocks per arbitration cycle */ PCP_ICR.U = 0x00000000; /* load PCP interrupt control register */ /* - the PCP warning mechanism is disabled */ PCP_ITR.U = 0x00000000; /* load PCP interrupt threshold register */ /* - type of service of PCP node 4 is CPU interrupt */ PCP_SRC4.U = 0x00001000; /* load service request control register 4 */ /* - type of service of PCP node 5 is CPU interrupt */ PCP_SRC5.U = 0x00001000; /* load service request control register 5 */ /* - type of service of PCP node 6 is CPU interrupt */ PCP_SRC6.U = 0x00001000; /* load service request control register 6 */ /* - type of service of PCP node 7 is CPU interrupt */ PCP_SRC7.U = 0x00001000; /* load service request control register 7 */ /* - type of service of PCP node 8 is CPU interrupt */ PCP_SRC8.U = 0x00001000; /* load service request control register 8 */ ts_initGPTAInt(); Port_Init(configPtr->bsw_driver.init_one.port_cfg); Adc_Init(configPtr->bsw_driver.init_one.adc_cfg); Fls_Init(configPtr->bsw_driver.init_one.fls_cfg); Gpt_Init(configPtr->bsw_driver.init_one.gpt_cfg); Pwm_Init(configPtr->bsw_driver.init_one.pwm_cfg); Spi_Init(configPtr->bsw_driver.init_one.spi_cfg); Wdg_Init(configPtr->bsw_driver.init_one.wdg_cfg); #ifdef ECUM_WDGM_INCLUDED WdgM_Init(configPtr->bsw_driver.init_one.wdgm_cfg); #endif /* setup end of init protected registers for OS */ ts_endinit_clear(); osInitProtected(); ts_endinit_set(); /* Overlay Ram: * Init registers and mem areas for switching from * working page (overlay ram) <-> reference page (flash) */ RAM_OverlayRamReset(); /* - the CPU interrupt system is globally disabled */ __enable(); Spi_SetAsyncMode(SPI_INTERRUPT_MODE); Adc_StartGroupConversion(0); Adc_StartGroupConversion(1); EcuM_SelectApplicationMode(OSDEFAULTAPPMODE); }