void sc8825_enable_timer_early(void) { /* enable timer & syscnt in global regs */ sci_glb_set(REG_GLB_GEN0, BIT_RTC_TMR_EB | BIT_RTC_SYST0_EB | BIT_TMR_EB | BIT_SYST0_EB); __sched_clock_init(26000000); }
void __init sci_enable_timer_early(void) { /* enable timer & syscnt in global regs */ int i = 0, j = 0; sci_glb_set(REG_AON_APB_APB_EB0, BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB); #if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB); for (i = 0; i < 4; i++) { #else sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB); for (i = 0; i < 2; i++) { #endif for (j = 0; j < 3; j++) { __gptimer_ctl(i, j, TIMER_DISABLE, 0); __raw_writel(TIMER_INT_CLR, TIMER_INT(i, j)); } } #if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L) /*timer1 fixed 32768 clk */ sched_clock_source_freq = 32768; #else /*timer2 clk source is from apb clk */ val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3; if (val == 0x1) sched_clock_source_freq = 76800000; else if (val == 0x2) sched_clock_source_freq = 96000000; else if (val == 0x3) sched_clock_source_freq = 128000000; else sched_clock_source_freq = 26000000; /*default setting */ #endif gptimer_clock_source_freq = sched_clock_source_freq; #if !defined (CONFIG_HAVE_ARM_ARCH_TIMER) __sched_clock_init(sched_clock_source_freq); #endif } u32 get_sys_cnt(void) { u32 val = 0; val = __raw_readl(SYSCNT_SHADOW_CNT); return val; }