void uart_reset()
{
if(arc_param->serial_disable)
return;
if(readl(P_UART_REG5(UART_PORT_CONS))==0){
unsigned uart_cfg = readl(P_UART_CONTROL(UART_PORT_CONS));
unsigned uart_misc = readl(P_AO_UART_MISC);
setbits_le32(P_AO_RTI_GEN_CNTL_REG0,1<<17);
clrbits_le32(P_AO_RTI_GEN_CNTL_REG0,1<<17);
__udelay(100);
writel(uart_cfg,P_UART_CONTROL(UART_PORT_CONS));
writel(uart_misc,P_AO_UART_MISC);
}else{
unsigned uart_cfg = readl(P_UART_CONTROL(UART_PORT_CONS));
unsigned uart_misc = readl(P_AO_UART_MISC);
unsigned new_baudrate=readl(P_UART_REG5(UART_PORT_CONS));
setbits_le32(P_AO_RTI_GEN_CNTL_REG0,1<<17);
clrbits_le32(P_AO_RTI_GEN_CNTL_REG0,1<<17);
__udelay(100);
writel(uart_cfg,P_UART_CONTROL(UART_PORT_CONS));
writel(uart_misc,P_AO_UART_MISC);
writel(new_baudrate,P_UART_REG5(UART_PORT_CONS));
__udelay(100);
}
}
void reset_mmc(void)
{
// writel((1 <<3), P_RESET1_REGISTER); // reset the whole MMC modules.
#ifdef POWER_DOWN_DDRPHY
APB_Wr(MMC_SOFT_RST, 0x0); // keep all MMC submodules in reset mode.
#endif
//Enable DDR DLL clock input from PLL.
writel(0xc0000080, P_MMC_CLK_CNTL); // @@@ select the final mux from PLL output directly.
writel(0xc00000c0, P_MMC_CLK_CNTL);
//enable the clock.
writel(0x400000c0, P_MMC_CLK_CNTL);
__udelay(10); // wait clock stable
//reset all sub module
APB_Wr(MMC_SOFT_RST, 0x0);
while((APB_Rd(MMC_RST_STS)&0xffff) != 0x0);
//deseart all reset.
APB_Wr(MMC_SOFT_RST, 0xffff);
while((APB_Rd(MMC_RST_STS)&0xffff) != 0xffff);
__udelay(100); // wait DLL lock.
}
void lowlevel_init(void* cur,void * target)
{
int i;
//close ddr
//gpiob_8
clrbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
clrbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//clrbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
//Adjust 1us timer base
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
//vcc_12v/24v power on GPIOX_70
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//backlight GPIOX_53
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
memory_pll_init(0,NULL);
//serial_put_dword(get_timer(0));
//serial_put_dword(readl(0xc1100000+0x200b*4));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
#if 1
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
do{
}while(ddr_init_test(0x6));
#endif
#endif
writel(0,P_WATCHDOG_TC);//disable Watchdog
// serial_puts("\nM2C Systemp Started\n");
}
void lowlevel_init(void* cur,void * target)
{
#if 0
if(cur != target) //r0!=r1
{
//running from spi
// take me as a spi rom boot mode
romboot_info->por_cfg = POR_INTL_SPI |
(READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
romboot_info->boot_id = 0;//boot from spi
/// Release pull up registers .
}
#endif
power_hold();
backlight_off();
//changed by Elvis, add uart rx pull up
//pull up LINUX_RX(B15--->GPIOE_19) reg (7422y v1.pdf)
//GPIOE_19(M1-Apps v25- 2010-07-19-BGA372_297-6.xls serach B15)
WRITE_CBUS_REG( PAD_PULL_UP_REG3, READ_CBUS_REG(PAD_PULL_UP_REG3) & ~(1<<2) ); // Meson-pull-up-down_table.xlsx ( GPIOE_19 is PAD_PULL_UP_REG3---0x203e 2bits)
//Adjust 1us timer base
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
memory_pll_init(0,NULL);
serial_puts("\nFirmware start at: ");
serial_put_dword(get_timer(0));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc())
{
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
// writel((0<<22)|1000000,P_WATCHDOG_TC);//enable Watchdog
unsigned por_cfg;
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test())
debug_rom(__FILE__,__LINE__);
#else
do{
}while(ddr_init_test());
#endif
serial_puts("\nFirmware started, now starting u-boot...");
}
void init_ddr_pll(void)
{
#if 0
reset_ddrpll:
//reset pll
writel(readl(P_HHI_DDR_PLL_CNTL)|(1<<29),P_HHI_DDR_PLL_CNTL);
writel(v_ddr_pll_cntl2,P_HHI_DDR_PLL_CNTL2);
writel(v_ddr_pll_cntl3,P_HHI_DDR_PLL_CNTL3);
writel(v_ddr_pll_cntl4,P_HHI_DDR_PLL_CNTL4);
writel(v_ddr_pll_cntl&0x7FFFFFFF,P_HHI_DDR_PLL_CNTL);
__udelay(1000);
while((readl(P_HHI_DDR_PLL_CNTL)&0x80000000) == 0)
{
clrbits_le32(P_AM_ANALOG_TOP_REG1,1);
setbits_le32(P_AM_ANALOG_TOP_REG1,1);
goto reset_ddrpll;
}
#endif /* 0 */
// Mike's code
int i;
reset_ddrpll:
i=0;
// reset bandgap
clrbits_le32(P_AM_ANALOG_TOP_REG1,1);
setbits_le32(P_AM_ANALOG_TOP_REG1,1);
__udelay(1000);
//reset pll
writel(readl(P_HHI_DDR_PLL_CNTL)|(1<<29),P_HHI_DDR_PLL_CNTL);
// program the PLL
writel(v_ddr_pll_cntl2,P_HHI_DDR_PLL_CNTL2);
writel(v_ddr_pll_cntl3,P_HHI_DDR_PLL_CNTL3);
writel(v_ddr_pll_cntl4,P_HHI_DDR_PLL_CNTL4);
//writel(v_ddr_pll_cntl&0x7FFFFFFF,P_HHI_DDR_PLL_CNTL);
writel((v_ddr_pll_cntl & ~(1<<30))|1<<29,P_HHI_DDR_PLL_CNTL);
writel(v_ddr_pll_cntl & ~(3<<29),P_HHI_DDR_PLL_CNTL);
do {
__udelay(1000);
if (i++ >= 100000)
goto reset_ddrpll; // excessive error, let's try again
} while((readl(P_HHI_DDR_PLL_CNTL)&0x80000000) == 0);
return;
}
static void clock_sync_cpu(struct clock_sync_data *sync)
{
atomic_dec(&sync->cpus);
enable_sync_clock();
/*
* This looks like a busy wait loop but it isn't. etr_sync_cpus
* is called on all other cpus while the TOD clocks is stopped.
* __udelay will stop the cpu on an enabled wait psw until the
* TOD is running again.
*/
while (sync->in_sync == 0) {
__udelay(1);
/*
* A different cpu changes *in_sync. Therefore use
* barrier() to force memory access.
*/
barrier();
}
if (sync->in_sync != 1)
/* Didn't work. Clear per-cpu in sync bit again. */
disable_sync_clock(NULL);
/*
* This round of TOD syncing is done. Set the clock comparator
* to the next tick and let the processor continue.
*/
fixup_clock_comparator(sync->fixup_cc);
}
static void wait_clock(unsigned clk,unsigned dest)
{
char * pszCLK[] = {
NULL,NULL,NULL,"DDR PLL","USB0 CLK","USB1 CLK",
"VID PLL","CLK81",NULL,NULL,NULL,"ETH RMII","VID2 PLL",
};
unsigned cur;
do{
cur=clk_util_clk_msr(clk);
serial_puts("\nSet [");
if(clk < (sizeof(pszCLK)/sizeof(pszCLK[0])) &&
pszCLK[clk])
serial_puts(pszCLK[clk]);
else
serial_puts("N/A");
serial_puts("] to ");
serial_put_dec(dest);
serial_puts("MHz now it is ");
//tolerance +/- 1
if((cur == dest-1) || (cur == dest+1))
serial_put_dec(dest);
else
serial_put_dec(cur);
serial_puts("MHz");
__udelay(100);
}while(cur<dest-1 || cur >dest+1);
serial_puts(" --> OK!\n");
}
static unsigned long wandboard_dram_init(void)
{
int cpu_type = __imx6_cpu_type();
unsigned long memsize;
switch (cpu_type) {
case IMX6_CPUTYPE_IMX6S:
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
memsize = SZ_512M;
break;
case IMX6_CPUTYPE_IMX6DL:
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
memsize = SZ_1G;
break;
case IMX6_CPUTYPE_IMX6Q:
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
memsize = SZ_2G;
break;
default:
return 0;
}
__udelay(100);
mmdc_do_write_level_calibration();
mmdc_do_dqs_calibration();
#ifdef DEBUG
mmdc_print_calibration_results();
#endif
return memsize;
}
static u32 _amd_erase_flash(u32 addr, u32 sector)
{
unsigned elapsed;
/* Issue erase */
*(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
*(volatile u32*)(addr + 0xaaa8) = 0x55555555;
*(volatile u32*)(addr + 0x5554) = 0x80808080;
/* And one unlock */
*(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
*(volatile u32*)(addr + 0xaaa8) = 0x55555555;
/* Sector erase command comes last */
*(volatile u32*)(addr + sector) = 0x30303030;
elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
elapsed = 0;
__udelay(50);
while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
elapsed += sc520_mmcr->swtmrmilli;
if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
*(volatile u32*)(addr) = 0xf0f0f0f0;
return 1;
}
}
*(volatile u32*)(addr) = 0xf0f0f0f0;
return 0;
}
STATIC_PREFIX void memory_pll_init(int argc, char * argv[])
{
pll_init(&__plls); //running under default freq now . Before we fixed the PLL stable problem
__udelay(1000);//delay 1 ms , wait pll ready
serial_init(__plls.uart);
}
void disable_mmc_req(void)
{
APB_Wr(MMC_REQ_CTRL,0X0);
while(APB_Rd(MMC_CHAN_STS) == 0){
__udelay(100);
}
}
void enable_retention(void)
{
//RENT_N/RENT_EN_N switch from 01 to 10 (2'b10 = ret_enable)
writel((readl(P_AO_RTI_PWR_CNTL_REG0)&(~(3<<16)))|(2<<16),P_AO_RTI_PWR_CNTL_REG0);
__udelay(200000);
//writel(readl(P_AO_RTI_PIN_MUX_REG)|(1<<20),P_AO_RTI_PIN_MUX_REG);
}
void disable_retention(void)
{
//RENT_N/RENT_EN_N switch from 10 to 01
writel((readl(P_AO_RTI_PWR_CNTL_REG0)&(~(3<<16)))|(1<<16),P_AO_RTI_PWR_CNTL_REG0);
__udelay(200);
//writel(readl(P_AO_RTI_PIN_MUX_REG)&(~(1<<20)),P_AO_RTI_PIN_MUX_REG);
}
int run_testpd(unsigned addr)
{
char cmd;
rbt_save_env();
/** copy ARM code*/
//change arm mapping
memcpy((void*)0x49008000,(void*)0x49000000,16*1024);
//remap arm memory
writel((0x49008000>>14)&0xf,P_AO_REMAP_REG0);
/** copy ARC code*/
//copy code to 49000000 and remap to zero
memcpy((void*)0x49008000,(void*)addr,16*1024);
writel(0x1<<4,P_AO_REMAP_REG1);
printf("start up ARC\n");
//switch to ARC jtag
// writel(0x51001,0xc8100030);
//reset arc
writel(RESET_ARC625,CBUS_REG_ADDR(RESET2_REGISTER));
__udelay(1000);
//enable arc
writel(1,CBUS_REG_ADDR(AUD_ARC_CTL));
writel(0,CBUS_REG_ADDR(AUD_ARC_CTL));
do{
printf("cmd >");
cmd = getc();
writel((unsigned)cmd,P_AO_RTI_STATUS_REG0);
__udelay(1000);
__udelay(1000);
if(cmd == 't'){
asm volatile ("wfi");
}
else{
while(readl(P_AO_RTI_STATUS_REG0) != 0)
{
__udelay(1000);
}
}
void load_nop(void)
{
writel((1 << 31) |
(DDR_RANK << 20) | //rank select
NOP_CMD
, P_UPCTL_MCMD_ADDR);
__udelay(1000);
while ( readl(P_UPCTL_MCMD_ADDR) & 0x80000000 ) {}
}
void mdelay (unsigned long msec)
{
int i,j;
for(i=0;i<msec;i++)
{
__udelay(1000);
}
}
void close_usb_phy_clock(int cfg)
{
dwc_otg_pullup(0);//disconnect
__udelay(20);
//dwc_otg_power_off_phy();//close phy
run_command("sleep 1", 0);//sleep sometime to improve pc compatibility!!
return;
}
static void ir_remocon_send_test(struct ir_remocon_data *data)
{
unsigned int period = 0;
int i;
period = MICRO_SEC / data->signal[0];
if (data->pwr_en == -1) {
regulator = regulator_get(NULL, "vled_3.3v");
if (IS_ERR(regulator))
goto out;
regulator_enable(regulator);
regulator_status = 1;
}
if (data->pwr_en != -1)
gpio_direction_output(data->pwr_en, 1);
local_irq_disable();
for (i = 1; i < MAX_SIZE; i++) {
if (data->signal[i] == 0)
break;
else if (data->signal[i] == 10) {
gpio_direction_output(data->gpio, 1);
__udelay(period);
} else if (data->signal[i] == 5) {
gpio_direction_output(data->gpio, 0);
__udelay(period);
}
}
local_irq_enable();
if (data->pwr_en != -1)
gpio_direction_output(data->pwr_en, 0);
if ((data->pwr_en == -1) && (regulator_status == 1)) {
regulator_force_disable(regulator);
regulator_put(regulator);
regulator_status = -1;
}
out: ;
}
void close_usb_phy_clock(int cfg)
{
cfg = cfg;//avoid compiler warning
dwc_otg_pullup(0);//disconnect
__udelay(20);
/*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!!
run_command("sleep 1", 0);//sleep sometime to improve pc compatibility!!
return;
}
void load_mrs(int mrs_num, int mrs_value)
{
writel((1 << 31) |
(DDR_RANK << 20) | //rank select
(mrs_num << 17) |
(mrs_value << 4) |
MRS_CMD
, P_UPCTL_MCMD_ADDR);
__udelay(1000);
while ( readl(P_UPCTL_MCMD_ADDR) & 0x80000000 ) {};
}
void udelay(unsigned long usec)
{
ulong kv;
do {
WATCHDOG_RESET();
kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
__udelay (kv);
usec -= kv;
} while(usec);
}
static void atmel_serial_init_internal(atmel_usart3_t *usart)
{
/*
* Just in case: drain transmitter register
* 1000us is enough for baudrate >= 9600
*/
if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
__udelay(1000);
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
}
static void atmel_serial_activate(atmel_usart3_t *usart)
{
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
/* 100us is enough for the new settings to be settled */
__udelay(100);
}
int run_arc(unsigned addr)
{
//char c;
/** copy ARM code*/
//change arm mapping
memcpy((void*)0x49008000,(void*)0x49000000,16*1024);
//remap arm memory
writel((0x49008000>>14)&0xf,P_AO_REMAP_REG0);
/** copy ARC code*/
//copy code to 49000000 and remap to zero
memcpy((void*)0x49008000,(void*)addr,16*1024);
writel(0x1<<4,P_AO_REMAP_REG1);
writel(0x7fffffff,P_AO_RTI_STATUS_REG0);
printf("start up ARC\n");
//switch to ARC jtag
// writel(0x51001,0xc8100030);
writel(1,P_AO_RTI_STATUS_REG1);
//reset arc
writel(RESET_ARC625,CBUS_REG_ADDR(RESET2_REGISTER));
__udelay(1000);
//enable arc
writel(1,CBUS_REG_ADDR(AUD_ARC_CTL));
writel(0,CBUS_REG_ADDR(AUD_ARC_CTL));
unsigned a,b;
unsigned timer_base;
a=b=0x7fffffff;
printf("ARM is Live\n");
timer_base=get_timer(0);
do{
a=readl(P_AO_RTI_STATUS_REG0);
if((a&0x80000000)|| ((a==b)&&(get_timer(timer_base)<10000000)))
{
continue;
}
timer_base=get_timer(0);
b=a;
printf("ARM is Live: %x",a);
switch(a&0xffff)
{
case 0:
printf("ARM Exit Sleep Mode\n");
break;
}
}while(a);
return 0;
}
int chip_reset(void)
{
#ifdef AML_BOOT_SPI
/* if uboot is on flash then boot agian from flash */
writel(WATCHDOG_ENABLE_MASK, IREG_WATCHDOG_CONTROL0);
#endif
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
WRITE_CBUS_REG(WATCHDOG_TC, 1 << 22 | 100); /*100*10uS=1ms*/
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
__udelay(10000);/**/
serial_puts("Chip watchdog reset error!!!please reset it by hardware\n");
while (1) ;
return 0;
}
void udelay( unsigned long usecs )
{
uint64_t later ;
uint64_t begin,offset;
if( clock_source_freezed )
return __udelay( usecs );
begin = rockchip_timer_read();
later = (rockchip_apb_clk*TIMER_MIN_PCLK);
later *= ((uint64_t)usecs);
do_div(later,USEC_PER_SEC);
if( later > TIMER_SCR_MASK ){
printk("%s::too much long delay=%ld us\n",__func__ , usecs );
return __udelay( usecs );
}
while( 1 ) {
nop();
offset = (rockchip_timer_read( )-begin) & TIMER_SCR_MASK ;
if( offset >= later) {
break;
}
}
}
STATIC_PREFIX void ddr_pll_init(struct ddr_set * ddr_setting)
{
int i;
writel(ddr_setting->ddr_pll_cntl|0x8000,P_HHI_DDR_PLL_CNTL);
writel(0x65e31ff,P_HHI_DDR_PLL_CNTL2);
writel(0x1649a941,P_HHI_DDR_PLL_CNTL3);
writel(ddr_setting->ddr_pll_cntl&(~(0x8000)),P_HHI_DDR_PLL_CNTL);
#if 0
for ( i = 0; i <= 1000; i ++) {
writel(ddr_setting->ddr_ctrl,P_MMC_DDR_CTRL); //
}
#else
__udelay(100);
while(!(readl(P_HHI_DDR_PLL_CNTL3)&(1<<31)));
#endif
}
static void hpll_load_en(void)
{
Write_reg_bits(P_HHI_VID_CLK_CNTL,1,19,1);
__udelay(1);
Write_reg_bits(P_HHI_VID_CLK_CNTL,7,0,3);
__udelay(1);
Write_reg_bits(P_HHI_VID_CLK_CNTL,1,16,3);
__udelay(1);
writel(0x1, P_ENCL_VIDEO_EN);
__udelay(100);
writel(0x0, P_ENCL_VIDEO_EN);
__udelay(100);
Write_reg_bits(P_HHI_VID_CLK_CNTL,0,16,3);
__udelay(10);
}
int rtc_hw_init(void)
{
losc_ctrl losctl = {0};
pr_info("%s(%d): start\n", __func__, __LINE__);
/*
* select rtc clock source
* on fpga board, internal 32k clk src is the default, and can not be changed
*/
losctl.clk32k_auto_swt_en = 0; /* disable auto switch */
losctl.osc32k_src_sel = 1; /* external 32768hz osc */
losctl.key_field = 0x16AA;
losctl.ext_losc_gsm = 2; /* external 32768hz osc gsm: 0b10 */
rtc_reg_list->losc_ctl = losctl;
__udelay(100);
/* check set result */
losctl = rtc_reg_list->losc_ctl;
if(1 != losctl.osc32k_src_sel) {
pr_err("%s(%d) err: set clksrc to external losc failed! rtc time will be wrong\n", __func__, __LINE__);
losc_err_flag = 1;
}
/* clear the alarm count value */
writel(0x00000000, &rtc_reg_list->a_cnt_dd_hh_mm_ss);
/* disable alarm, not generate irq pending */
writel(0x00000000, &rtc_reg_list->a_enable);
/* disable alarm week/cnt irq, unset to cpu */
writel(0x00000000, &rtc_reg_list->a_irq_enable);
writel(0x00000000, ALARM_CONFIG_REG);
/* clear alarm week/cnt irq pending */
writel(3, &rtc_reg_list->a_irq_status);
pr_info("%s(%d): end\n", __func__, __LINE__);
return 0;
}
static void __efuse_write_byte( unsigned long addr, unsigned long data )
{
#ifndef CONFIG_MESON_TRUSTZONE
#ifdef EFUSE_DEBUG
char *p = (char*)debug_buf;
p[addr] = data;
return;
#endif
//printf("addr=%d, data=%x\n", addr, data);
unsigned long auto_wr_is_enabled = 0;
//set efuse PD=0
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, 0, 27, 1);
if ( READ_EFUSE_REG( P_EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_WR_ENABLE_BIT ) )
{
auto_wr_is_enabled = 1;
}
else
{
/* temporarily enable Write mode */
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, CNTL1_AUTO_WR_ENABLE_ON,
CNTL1_AUTO_WR_ENABLE_BIT, CNTL1_AUTO_WR_ENABLE_SIZE );
}
#if defined(CONFIG_M8) || defined(CONFIG_M8B)
unsigned int byte_sel = addr % 4;
addr = addr / 4;
/* write the address */
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, addr,
CNTL1_BYTE_ADDR_BIT, CNTL1_BYTE_ADDR_SIZE );
//auto write byte select (0-3), for m8
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL3, byte_sel,
CNTL1_AUTO_WR_START_BIT, 2 );
#else
/* write the address */
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, addr,
CNTL1_BYTE_ADDR_BIT, CNTL1_BYTE_ADDR_SIZE );
#endif
/* set starting byte address */
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_ON,
CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_OFF,
CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
/* write the byte */
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, data,
CNTL1_BYTE_WR_DATA_BIT, CNTL1_BYTE_WR_DATA_SIZE );
/* start the write process */
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, CNTL1_AUTO_WR_START_ON,
CNTL1_AUTO_WR_START_BIT, CNTL1_AUTO_WR_START_SIZE );
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, CNTL1_AUTO_WR_START_OFF,
CNTL1_AUTO_WR_START_BIT, CNTL1_AUTO_WR_START_SIZE );
/* dummy read */
READ_EFUSE_REG(P_EFUSE_CNTL1 );
while ( READ_EFUSE_REG(P_EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_WR_BUSY_BIT ))
{
__udelay(1);
}
/* if auto write wasn't enabled and we enabled it, then disable it upon exit */
if (auto_wr_is_enabled == 0 )
{
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, CNTL1_AUTO_WR_ENABLE_OFF,
CNTL1_AUTO_WR_ENABLE_BIT, CNTL1_AUTO_WR_ENABLE_SIZE );
}
//set efuse PD=1
WRITE_EFUSE_REG_BITS( P_EFUSE_CNTL1, 1, 27, 1);
#endif // endif trustzone
}
