mali_bool power_test_check()
{
if( power_test_flag )
{
_mali_uk_pmm_message_s event = {
NULL,
0,
1 };
event.id = power_test_event;
power_test_flag = MALI_FALSE;
/* Send event */
_mali_ukk_pmm_event_message( &event );
/* Switch to next event to test */
if( power_test_event == MALI_PMM_EVENT_OS_POWER_DOWN )
{
power_test_event = MALI_PMM_EVENT_OS_POWER_UP;
}
else
{
power_test_event = MALI_PMM_EVENT_OS_POWER_DOWN;
}
_mali_osk_timer_add( power_test_timer, 5000 );
return MALI_TRUE;
}
return MALI_FALSE;
}
void power_test_start()
{
power_test_timer = _mali_osk_timer_init();
_mali_osk_timer_setcallback( power_test_timer, power_test_callback, NULL );
/* First event is power down */
power_test_event = MALI_PMM_EVENT_OS_POWER_DOWN;
_mali_osk_timer_add( power_test_timer, 10000 );
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job)
{
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_FRAME, frame_registers, MALI200_NUM_REGS_FRAME, mali_frame_registers_reset_values);
_mali_osk_mem_barrier();
if (0 != sub_job)
{
/*
* There are two frame registers which are different for each sub job.
* For the first sub job, these are correctly represented in the frame register array,
* but we need to patch these for all other sub jobs
*/
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job));
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_STACK/4]);
}
if (wb0_registers[0]) /* M200_WB0_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, 0, mali_wb_registers_reset_values[0] );
}
if (wb1_registers[0]) /* M200_WB1_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, 0, mali_wb_registers_reset_values[0] );
}
if (wb2_registers[0]) /* M200_WB2_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, 0, mali_wb_registers_reset_values[0] );
}
/* This selects which performance counters we are reading */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
/* global_config has enabled HW counters, this will override anything specified by user space */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
}
else
{
/* Use HW counters from job object, if any */
u32 perf_counter_flag = mali_pp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_pp_job_get_perf_counter_src0(job);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_pp_job_get_perf_counter_src1(job);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
/* Adding barrier to make sure all rester writes are finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
/* Adding barrier to make sure previous rester writes is finished */
_mali_osk_write_mem_barrier();
/* Setup the timeout timer value and save the job id for the job running on the pp core */
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_pp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH, mali_pp_job_get_frame_builder_id(job), mali_pp_job_get_flush_id(job), 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id), mali_pp_job_get_pid(job), mali_pp_job_get_tid(job), 0, 0, 0);
#endif
core->running_job = job;
core->running_sub_job = sub_job;
}
static int subsystem_mali200_irq_handler_bottom_half(struct mali_core_renderunit* core)
{
u32 irq_readout;
u32 current_tile_addr;
u32 core_status;
mali_core_job * job;
mali200_job * job200;
job = core->current_job;
job200 = GET_JOB200_PTR(job);
if (mali_benchmark) {
irq_readout = MALI200_REG_VAL_IRQ_END_OF_FRAME;
current_tile_addr = 0;
core_status = 0;
} else {
irq_readout = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & MALI200_REG_VAL_IRQ_MASK_USED;
current_tile_addr = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR);
core_status = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_STATUS);
}
if (NULL == job)
{
MALI_DEBUG_ASSERT(CORE_IDLE==core->state);
if ( 0 != irq_readout )
{
MALI_PRINT_ERROR(("Interrupt from a core not running a job. IRQ: 0x%04x Status: 0x%04x", irq_readout, core_status));
}
return JOB_STATUS_END_UNKNOWN_ERR;
}
MALI_DEBUG_ASSERT(CORE_IDLE!=core->state);
job200->irq_status |= irq_readout;
MALI_DEBUG_PRINT_IF( 3, ( 0 != irq_readout ),
("Mali PP: Job: 0x%08x IRQ RECEIVED Rawstat: 0x%x Tile_addr: 0x%x Status: 0x%x\n",
(u32)job200->user_input.user_job_ptr, irq_readout ,current_tile_addr ,core_status));
if ( MALI200_REG_VAL_IRQ_END_OF_FRAME & irq_readout)
{
#if defined(USING_MALI200)
mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES);
#endif
if (0 != job200->user_input.perf_counter_flag )
{
if (job200->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE) )
{
job200->perf_counter0 = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
job200->perf_counter1 = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
}
#if defined(USING_MALI400_L2_CACHE)
if (job200->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
{
u32 src0;
u32 val0;
u32 src1;
u32 val1;
mali_kernel_l2_cache_get_perf_counters(&src0, &val0, &src1, &val1);
if (job200->perf_counter_l2_src0 == src0)
{
job200->perf_counter_l2_val0_raw = val0;
job200->perf_counter_l2_val0 = val0 - job200->perf_counter_l2_val0;
}
else
{
job200->perf_counter_l2_val0_raw = 0;
job200->perf_counter_l2_val0 = 0;
}
if (job200->perf_counter_l2_src1 == src1)
{
job200->perf_counter_l2_val1_raw = val1;
job200->perf_counter_l2_val1 = val1 - job200->perf_counter_l2_val1;
}
else
{
job200->perf_counter_l2_val1_raw = 0;
job200->perf_counter_l2_val1 = 0;
}
}
#endif
}
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number),
job200->perf_counter0, job200->perf_counter1,
job200->user_input.perf_counter_src0 | (job200->user_input.perf_counter_src1 << 8)
#if defined(USING_MALI400_L2_CACHE)
| (job200->user_input.perf_counter_l2_src0 << 16) | (job200->user_input.perf_counter_l2_src1 << 24),
job200->perf_counter_l2_val0_raw, job200->perf_counter_l2_val1_raw
#else
, 0, 0
#endif
);
#endif
#if MALI_STATE_TRACKING
_mali_osk_atomic_inc(&job->session->jobs_ended);
#endif
return JOB_STATUS_END_SUCCESS; /* reschedule */
}
/* Overall SW watchdog timeout or (time to do hang checking and progress detected)? */
else if (
(CORE_WATCHDOG_TIMEOUT == core->state) ||
((CORE_HANG_CHECK_TIMEOUT == core->state) && (current_tile_addr == job200->last_tile_list_addr))
)
{
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status */
#endif
/* no progress detected, killed by the watchdog */
MALI_DEBUG_PRINT(2, ("M200: SW-Timeout Rawstat: 0x%x Tile_addr: 0x%x Status: 0x%x.\n", irq_readout ,current_tile_addr ,core_status) );
/* In this case will the system outside cleanup and reset the core */
#if MALI_STATE_TRACKING
_mali_osk_atomic_inc(&job->session->jobs_ended);
#endif
return JOB_STATUS_END_HANG;
}
/* HW watchdog triggered or an existing hang check passed? */
else if ((CORE_HANG_CHECK_TIMEOUT == core->state) || (irq_readout & job200->active_mask & MALI200_REG_VAL_IRQ_HANG))
{
/* check interval in ms */
u32 timeout = mali_core_hang_check_timeout_get();
MALI_DEBUG_PRINT(3, ("M200: HW/SW Watchdog triggered, checking for progress in %d ms\n", timeout));
job200->last_tile_list_addr = current_tile_addr;
/* hw watchdog triggered, set up a progress checker every HANGCHECK ms */
_mali_osk_timer_add(core->timer_hang_detection, _mali_osk_time_mstoticks(timeout));
job200->active_mask &= ~MALI200_REG_VAL_IRQ_HANG; /* ignore the hw watchdoig from now on */
mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, irq_readout & ~MALI200_REG_VAL_IRQ_HANG);
mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, job200->active_mask);
return JOB_STATUS_CONTINUE_RUN; /* not finished */
}
/* No irq pending, core still busy */
else if ((0 == (irq_readout & MALI200_REG_VAL_IRQ_MASK_USED)) && ( 0 != (core_status & MALI200_REG_VAL_STATUS_RENDERING_ACTIVE)))
{
mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, irq_readout);
mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, job200->active_mask);
return JOB_STATUS_CONTINUE_RUN; /* Not finished */
}
else
{
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status */
#endif
MALI_DEBUG_PRINT(1, ("Mali PP: Job: 0x%08x CRASH? Rawstat: 0x%x Tile_addr: 0x%x Status: 0x%x\n",
(u32)job200->user_input.user_job_ptr, irq_readout ,current_tile_addr ,core_status) ) ;
if (irq_readout & MALI200_REG_VAL_IRQ_BUS_ERROR)
{
u32 bus_error = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS);
MALI_DEBUG_PRINT(1, ("Bus error status: 0x%08X\n", bus_error));
MALI_DEBUG_PRINT_IF(1, (bus_error & 0x01), ("Bus write error from id 0x%02x\n", (bus_error>>2) & 0x0F));
MALI_DEBUG_PRINT_IF(1, (bus_error & 0x02), ("Bus read error from id 0x%02x\n", (bus_error>>6) & 0x0F));
MALI_DEBUG_PRINT_IF(1, (0 == (bus_error & 0x03)), ("Bus error but neither read or write was set as the error reason\n"));
(void)bus_error;
}
#if MALI_STATE_TRACKING
_mali_osk_atomic_inc(&job->session->jobs_ended);
#endif
return JOB_STATUS_END_UNKNOWN_ERR; /* reschedule */
}
void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 startcmd = 0;
u32 *frame_registers = mali_gp_job_get_frame_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
if (mali_gp_job_has_vs_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
}
if (mali_gp_job_has_plbu_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
}
MALI_DEBUG_ASSERT(0 != startcmd);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
#if PROFILING_PRINT_L2_HITRATE_ON_GP_FINISH
{
mali_l2_cache_core_set_counter_src0(mali_l2_cache_core_get_glob_l2_core(0), 20);
mali_l2_cache_core_set_counter_src1(mali_l2_cache_core_get_glob_l2_core(0), 21);
}
#endif
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
else
{
u32 perf_counter_flag = mali_gp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_gp_job_get_perf_counter_src0(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_gp_job_get_perf_counter_src1(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
_mali_osk_write_mem_barrier();
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
_mali_osk_write_mem_barrier();
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_gp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH,
job->frame_builder_id, job->flush_id, 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0), job->pid, job->tid, 0, 0, 0);
#endif
core->running_job = job;
}
void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 startcmd = 0;
u32 *frame_registers = mali_gp_job_get_frame_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
if (mali_gp_job_has_vs_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
}
if (mali_gp_job_has_plbu_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
}
MALI_DEBUG_ASSERT(0 != startcmd);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
#if PROFILING_PRINT_L2_HITRATE_ON_GP_FINISH
{
/* Read hits and Read misses*/
mali_l2_cache_core_set_counter_src0(mali_l2_cache_core_get_glob_l2_core(0), 20);
mali_l2_cache_core_set_counter_src1(mali_l2_cache_core_get_glob_l2_core(0), 21);
}
#endif
/* This selects which performance counters we are reading */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
/* global_config has enabled HW counters, this will override anything specified by user space */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
else
{
/* Use HW counters from job object, if any */
u32 perf_counter_flag = mali_gp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_gp_job_get_perf_counter_src0(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_gp_job_get_perf_counter_src1(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
/* Setup the timeout timer value and save the job id for the job running on the gp core */
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_gp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH,
mali_gp_job_get_frame_builder_id(job), mali_gp_job_get_flush_id(job), 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0), mali_gp_job_get_pid(job), mali_gp_job_get_tid(job), 0, 0, 0);
#endif
core->running_job = job;
}
void mali_control_timer_add(u32 timeout)
{
_mali_osk_timer_add(mali_control_timer, _mali_osk_time_mstoticks(timeout));
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job)
{
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, frame_registers, MALI200_NUM_REGS_FRAME);
if (0 != sub_job)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job));
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job));
}
if (wb0_registers[0])
{
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, MALI200_NUM_REGS_WBx);
}
if (wb1_registers[0])
{
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, MALI200_NUM_REGS_WBx);
}
if (wb2_registers[0])
{
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, MALI200_NUM_REGS_WBx);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
}
else
{
u32 perf_counter_flag = mali_pp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_pp_job_get_perf_counter_src0(job);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_pp_job_get_perf_counter_src1(job);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
_mali_osk_write_mem_barrier();
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
_mali_osk_write_mem_barrier();
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_pp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH, job->frame_builder_id, job->flush_id, 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id), job->pid, job->tid, 0, 0, 0);
#endif
core->running_job = job;
core->running_sub_job = sub_job;
}
