//review again
struct sk_buff * dev_alloc_skb(unsigned int size)
{
struct sk_buff *skb=NULL;
u8 *data=NULL;
//skb = (struct sk_buff *)_rtw_zmalloc(sizeof(struct sk_buff)); // for skb->len, etc.
skb = (struct sk_buff *)_rtw_malloc(sizeof(struct sk_buff));
if(!skb)
goto out;
data = _rtw_malloc(size);
if(!data)
goto nodata;
skb->head = (unsigned char*)data;
skb->data = (unsigned char*)data;
skb->tail = (unsigned char*)data;
skb->end = (unsigned char*)data + size;
skb->len = 0;
//printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head);
out:
return skb;
nodata:
_rtw_mfree((u8 *)skb, sizeof(struct sk_buff));
skb = NULL;
goto out;
}
u8 *_rtw_zmalloc(u32 sz)
{
u8 *pbuf = _rtw_malloc(sz);
if (pbuf != NULL)
memset(pbuf, 0, sz);
return pbuf;
}
u8* os_malloc(u32 sz)
{
int free_heap_size = rtw_getFreeHeapSize();
u8 *pbuf = _rtw_malloc(sz);
#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK
add_mem_usage(&wpa_mem_table, pbuf, sz, &wpa_mem_used_num, MEM_MONITOR_FLAG_WPAS);
#else
add_mem_usage(NULL, pbuf, sz, NULL, MEM_MONITOR_FLAG_WPAS);
#endif
if(min_free_heap_size > free_heap_size)
min_free_heap_size = free_heap_size;
return pbuf;
}
u8* _rtw_zmalloc(u32 sz)
{
u8 *pbuf = _rtw_malloc(sz);
if (pbuf != NULL) {
#ifdef PLATFORM_LINUX
memset(pbuf, 0, sz);
#endif
}
return pbuf;
}
inline u8* dbg_rtw_malloc(u32 sz, const char *func, int line)
{
u8 *p;
if((sz)>4096)
DBG_871X("DBG_MEM_ALLOC !!!!!!!!!!!!!! %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p=_rtw_malloc((sz));
rtw_update_mem_stat(
p ? MEM_STAT_PHY_ALLOC_SUCCESS : MEM_STAT_PHY_ALLOC_FAIL
, sz
);
return p;
}
inline u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
{
u8 *p;
if (match_mstat_sniff_rules(flags, sz))
DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p=_rtw_malloc((sz));
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, sz
);
return p;
}
u8* _rtw_zmalloc(u32 sz)
{
u8 *pbuf = _rtw_malloc(sz);
if (pbuf != NULL) {
#ifdef PLATFORM_LINUX
memset(pbuf, 0, sz);
#endif
#ifdef PLATFORM_WINDOWS
NdisFillMemory(pbuf, sz, 0);
#endif
}
return pbuf;
}
inline u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
{
u8 *p;
//if(sz>=153 && sz<=306)
// DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
//if((sz)>4096)
// DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p=_rtw_malloc((sz));
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, sz
);
return p;
}
u8* _rtw_zmalloc(u32 sz)
{
#ifdef PLATFORM_FREEBSD
return malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT);
#else // PLATFORM_FREEBSD
u8 *pbuf = _rtw_malloc(sz);
if (pbuf != NULL) {
#ifdef PLATFORM_LINUX
memset(pbuf, 0, sz);
#endif
#ifdef PLATFORM_WINDOWS
NdisFillMemory(pbuf, sz, 0);
#endif
}
return pbuf;
#endif // PLATFORM_FREEBSD
}
inline u8* dbg_rtw_malloc(u32 sz, const char *func, int line)
{
if((sz)>4096)
DBG_871X("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!%s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
return _rtw_malloc((sz));
}
void sd_int_dpc(PADAPTER padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (pHalData->sdio_hisr & SDIO_HISR_CPWM1)
{
struct reportpwrstate_parm report;
_sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state);
#ifdef CONFIG_LPS_LCLK
//88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow.
//modify by Thomas. 2012/4/2.
#ifdef CONFIG_EXT_CLK //for sprd
if(report.state & BIT(4)) //indicate FW entering 32k
{
u8 chk_cnt = 0;
do{
if(_sdio_read8(padapter, 0x90)&BIT(0))//FW in 32k already
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
if(pwrpriv->rpwm < PS_STATE_S2)
{
//DBG_871X("disable ext clk when FW in LPS-32K already!\n");
EnableGpio5ClockReq(padapter, _TRUE, 0);
}
break;
}
chk_cnt++;
}while(chk_cnt<10);
if(chk_cnt==10)
{
DBG_871X("polling fw in 32k already, fail!\n");
}
}
else //indicate fw leaving 32K
#endif //CONFIG_EXT_CLK
{
report.state |= PS_STATE_S2;
//cpwm_int_hdl(padapter, &report);
_set_workitem(&padapter->pwrctrlpriv.cpwm_event);
}
#endif
}
#ifdef CONFIG_WOWLAN
if (pHalData->sdio_hisr & SDIO_HISR_CPWM2) {
u32 value;
value = rtw_read32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR);
DBG_871X_LEVEL(_drv_always_, "Reset SDIO HISR(0x%08x) original:0x%08x\n",
SDIO_LOCAL_BASE+SDIO_REG_HISR, value);
value |= BIT19;
rtw_write32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR, value);
value = rtw_read8(padapter, SDIO_LOCAL_BASE+SDIO_REG_HIMR+2);
DBG_871X_LEVEL(_drv_always_, "Reset SDIO HIMR CPWM2(0x%08x) original:0x%02x\n",
SDIO_LOCAL_BASE+SDIO_REG_HIMR + 2, value);
}
#endif
if (pHalData->sdio_hisr & SDIO_HISR_TXERR)
{
u8 *status;
u32 addr;
status = _rtw_malloc(4);
if (status)
{
addr = REG_TXDMA_STATUS;
HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr);
_sd_read(&adapter_to_dvobj(padapter)->intf_data, addr, 4, status);
_sd_write(&adapter_to_dvobj(padapter)->intf_data, addr, 4, status);
DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status));
_rtw_mfree(status, 4);
} else {
DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__);
}
}
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT)
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
if (pHalData->sdio_hisr & (SDIO_HISR_TXBCNOK|SDIO_HISR_TXBCNERR))
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0 //for debug
if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT)
DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__);
if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK)
DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__);
if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR)
DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__);
#endif
if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#ifdef CONFIG_CONCURRENT_MODE
if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
}
#endif //CONFIG_INTERRUPT_BASED_TXBCN
#ifdef CONFIG_EXT_CLK
if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if(check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
{
//DBG_8192C("BCNERLY_INT for enabling ext clk\n");
EnableGpio5ClockReq(padapter, _TRUE, 1);
}
}
#endif //CONFIG_EXT_CLK
if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD)
{
DBG_8192C("%s: C2H Command\n", __func__);
}
if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST)
{
struct recv_buf *precvbuf;
//DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize);
pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST;
#ifdef CONFIG_MAC_LOOPBACK_DRIVER
sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize);
#else
do {
//Sometimes rx length will be zero. driver need to use cmd53 read again.
if(pHalData->SdioRxFIFOSize == 0)
{
u8 data[4];
_sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data);
pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data);
}
if(pHalData->SdioRxFIFOSize)
{
precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize);
pHalData->SdioRxFIFOSize = 0;
if (precvbuf)
sd_rxhandler(padapter, precvbuf);
else
break;
}
else
break;
#ifdef CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP
} while (0);
#else
} while (1);
#endif
#endif
}
//
// Description:
// Download 8192C firmware code.
//
//
int FirmwareDownload92C(
IN PADAPTER Adapter
)
{
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
char R92CFwImageFileName_TSMC[] ={RTL8192C_FW_TSMC_IMG};
char R92CFwImageFileName_UMC[] ={RTL8192C_FW_UMC_IMG};
char R8723FwImageFileName_UMC[] ={RTL8723_FW_UMC_IMG};
char * FwImage;
u32 FwImageLen;
char* pFwImageFileName;
//vivi, merge 92c and 92s into one driver, 20090817
//vivi modify this temply, consider it later!!!!!!!!
//PRT_FIRMWARE pFirmware = GET_FIRMWARE_819X(Adapter);
//PRT_FIRMWARE_92C pFirmware = GET_FIRMWARE_8192C(Adapter);
PRT_FIRMWARE_92C pFirmware = NULL;
PRT_8192C_FIRMWARE_HDR pFwHdr = NULL;
u8 *pFirmwareBuf;
u32 FirmwareLen;
pFirmware = (PRT_FIRMWARE_92C)_rtw_malloc(sizeof(RT_FIRMWARE_92C));
if(!pFirmware)
{
rtStatus = _FAIL;
goto Exit;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:%s\n", pFwImageFileName));
#ifdef CONFIG_EMBEDDED_FWIMG
pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
#else
pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
#endif
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
if(IS_VENDOR_UMC_A_CUT(pHalData->VersionID) && !IS_92C_SERIAL(pHalData->VersionID))// UMC , 8188
{
pFwImageFileName = R92CFwImageFileName_UMC;
FwImage = Rtl819XFwUMCImageArray;
FwImageLen = UMCImgArrayLength;
DBG_871X(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_UMC\n");
}
else
{
pFwImageFileName = R92CFwImageFileName_TSMC;
FwImage = Rtl819XFwTSMCImageArray;
FwImageLen = TSMCImgArrayLength;
DBG_871X(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_TSMC\n");
}
}
else
{
#if 0
pFwImageFileName = TestChipFwFile;
FwImage = Rtl8192CTestFwImg;
FwImageLen = Rtl8192CTestFwImgLen;
RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:Rtl8192CTestFwImg\n"));
#endif
}
switch(pFirmware->eFWSource)
{
case FW_SOURCE_IMG_FILE:
//TODO:load fw bin file
break;
case FW_SOURCE_HEADER_FILE:
if(TSMCImgArrayLength > FW_8192C_SIZE){
rtStatus = _FAIL;
//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE) );
DBG_871X("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE);
goto Exit;
}
_rtw_memcpy(pFirmware->szFwBuffer, FwImage, FwImageLen);
pFirmware->ulFwLength = FwImageLen;
break;
}
pFirmwareBuf = pFirmware->szFwBuffer;
FirmwareLen = pFirmware->ulFwLength;
// To Check Fw header.
pFwHdr = (PRT_8192C_FIRMWARE_HDR)pFirmware->szFwBuffer;
pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion);
//RT_TRACE(COMP_INIT, DBG_LOUD, (" FirmwareVersion(%#x), Signature(%#x)\n",
// Adapter->MgntInfo.FirmwareVersion, pFwHdr->Signature));
DBG_8192C("fw_ver=v%d, fw_subver=%d, sig=0x%x\n",
pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, le16_to_cpu(pFwHdr->Signature)&0xFFF0);
if(IS_FW_HEADER_EXIST(pFwHdr))
{
//RT_TRACE(COMP_INIT, DBG_LOUD,("Shift 32 bytes for FW header!!\n"));
pFirmwareBuf = pFirmwareBuf + 32;
FirmwareLen = FirmwareLen -32;
}
// Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself,
// or it will cause download Fw fail. 2010.02.01. by tynli.
if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7) //8051 RAM code
{
DBG_8192C("8051 in Ram......prepare to reset by itself\n");
_FirmwareSelfReset(Adapter);
rtw_write8(Adapter, REG_MCUFWDL, 0x00);
}
_FWDownloadEnable(Adapter, _TRUE);
_WriteFW(Adapter, pFirmwareBuf, FirmwareLen);
_FWDownloadEnable(Adapter, _FALSE);
rtStatus = _FWFreeToGo(Adapter);
if(_SUCCESS != rtStatus){
//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("DL Firmware failed!\n") );
goto Exit;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, (" Firmware is ready to run!\n"));
Exit:
if(pFirmware)
_rtw_mfree((u8*)pFirmware, sizeof(RT_FIRMWARE_92C));
//RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n"));
return rtStatus;
}
void sd_int_dpc(PADAPTER padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (pHalData->sdio_hisr & SDIO_HISR_CPWM1)
{
struct reportpwrstate_parm report;
_sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state);
#ifdef CONFIG_LPS_LCLK
//88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow.
//modify by Thomas. 2012/4/2.
report.state |= PS_STATE_S2;
//cpwm_int_hdl(padapter, &report);
_set_workitem(&padapter->pwrctrlpriv.cpwm_event);
#endif
}
if (pHalData->sdio_hisr & SDIO_HISR_TXERR)
{
u8 *status;
u32 addr;
status = _rtw_malloc(4);
if (status)
{
addr = REG_TXDMA_STATUS;
HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr);
_sd_read(&padapter->dvobjpriv.intf_data, addr, 4, status);
_sd_write(&padapter->dvobjpriv.intf_data, addr, 4, status);
printk("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status));
_rtw_mfree(status, 4);
} else {
printk("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__);
}
}
if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK)
{
printk("%s: SDIO_HISR_TXBCNOK\n", __func__);
}
if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR)
{
printk("%s: SDIO_HISR_TXBCNERR\n", __func__);
}
if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD)
{
printk("%s: C2H Command\n", __func__);
}
if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST)
{
struct recv_buf *precvbuf;
//printk("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize);
pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST;
#ifdef CONFIG_MAC_LOOPBACK_DRIVER
sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize);
#else
//Sometimes rx length will be zero. driver need to use cmd53 read again.
if(pHalData->SdioRxFIFOSize == 0)
{
u8 data[4];
_sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data);
pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data);
}
if(pHalData->SdioRxFIFOSize)
{
precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize);
if (precvbuf)
sd_rxhandler(padapter, precvbuf);
pHalData->SdioRxFIFOSize = 0;
}
#endif
}
}
