static void __init setup_nonnuma(void) { unsigned long top_of_ram = lmb_end_of_DRAM(); unsigned long total_ram = lmb_phys_mem_size(); unsigned long i; printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", top_of_ram, total_ram); printk(KERN_INFO "Memory hole size: %ldMB\n", (top_of_ram - total_ram) >> 20); if (!numa_memory_lookup_table) { long entries = top_of_ram >> MEMORY_INCREMENT_SHIFT; numa_memory_lookup_table = (char *)abs_to_virt(lmb_alloc(entries * sizeof(char), 1)); for (i = 0; i < entries ; i++) numa_memory_lookup_table[i] = ARRAY_INITIALISER; }
u64 hipz_h_register_rpage_mr(const struct ipz_adapter_handle adapter_handle, const struct ehca_mr *mr, const u8 pagesize, const u8 queue_type, const u64 logical_address_of_page, const u64 count) { u64 ret; if (unlikely(ehca_debug_level >= 3)) { if (count > 1) { u64 *kpage; int i; kpage = (u64 *)abs_to_virt(logical_address_of_page); for (i = 0; i < count; i++) ehca_gen_dbg("kpage[%d]=%p", i, (void *)kpage[i]); } else ehca_gen_dbg("kpage=%p", (void *)logical_address_of_page); } if ((count > 1) && (logical_address_of_page & (EHCA_PAGESIZE-1))) { ehca_gen_err("logical_address_of_page not on a 4k boundary " "adapter_handle=%llx mr=%p mr_handle=%llx " "pagesize=%x queue_type=%x " "logical_address_of_page=%llx count=%llx", adapter_handle.handle, mr, mr->ipz_mr_handle.handle, pagesize, queue_type, logical_address_of_page, count); ret = H_PARAMETER; } else ret = hipz_h_register_rpage(adapter_handle, pagesize, queue_type, mr->ipz_mr_handle.handle, logical_address_of_page, count); return ret; }
static void trace_send_wr_ud(const struct ib_send_wr *send_wr) { int idx; int j; while (send_wr) { struct ib_mad_hdr *mad_hdr = send_wr->wr.ud.mad_hdr; struct ib_sge *sge = send_wr->sg_list; ehca_gen_dbg("send_wr#%x wr_id=%lx num_sge=%x " "send_flags=%x opcode=%x", idx, send_wr->wr_id, send_wr->num_sge, send_wr->send_flags, send_wr->opcode); if (mad_hdr) { ehca_gen_dbg("send_wr#%x mad_hdr base_version=%x " "mgmt_class=%x class_version=%x method=%x " "status=%x class_specific=%x tid=%lx " "attr_id=%x resv=%x attr_mod=%x", idx, mad_hdr->base_version, mad_hdr->mgmt_class, mad_hdr->class_version, mad_hdr->method, mad_hdr->status, mad_hdr->class_specific, mad_hdr->tid, mad_hdr->attr_id, mad_hdr->resv, mad_hdr->attr_mod); } for (j = 0; j < send_wr->num_sge; j++) { u8 *data = (u8 *)abs_to_virt(sge->addr); ehca_gen_dbg("send_wr#%x sge#%x addr=%p length=%x " "lkey=%x", idx, j, data, sge->length, sge->lkey); /* assume length is n*16 */ ehca_dmp(data, sge->length, "send_wr#%x sge#%x", idx, j); sge++; } /* eof for j */ idx++; send_wr = send_wr->next; } /* eof while send_wr */ }
static int __init parse_numa_properties(void) { struct device_node *cpu = NULL; struct device_node *memory = NULL; int depth; int max_domain = 0; long entries = lmb_end_of_DRAM() >> MEMORY_INCREMENT_SHIFT; unsigned long i; if (strstr(saved_command_line, "numa=off")) { printk(KERN_WARNING "NUMA disabled by user\n"); return -1; } numa_memory_lookup_table = (char *)abs_to_virt(lmb_alloc(entries * sizeof(char), 1)); for (i = 0; i < entries ; i++) numa_memory_lookup_table[i] = ARRAY_INITIALISER; depth = find_min_common_depth(); printk(KERN_INFO "NUMA associativity depth for CPU/Memory: %d\n", depth); if (depth < 0) return depth; for_each_cpu(i) { int numa_domain; cpu = find_cpu_node(i); if (cpu) { numa_domain = of_node_numa_domain(cpu, depth); of_node_put(cpu); if (numa_domain >= MAX_NUMNODES) { /* * POWER4 LPAR uses 0xffff as invalid node, * dont warn in this case. */ if (numa_domain != 0xffff) printk(KERN_ERR "WARNING: cpu %ld " "maps to invalid NUMA node %d\n", i, numa_domain); numa_domain = 0; } } else { printk(KERN_ERR "WARNING: no NUMA information for " "cpu %ld\n", i); numa_domain = 0; } node_set_online(numa_domain); if (max_domain < numa_domain) max_domain = numa_domain; map_cpu_to_node(i, numa_domain); } memory = NULL; while ((memory = of_find_node_by_type(memory, "memory")) != NULL) { unsigned long start; unsigned long size; int numa_domain; int ranges; unsigned int *memcell_buf; unsigned int len; memcell_buf = (unsigned int *)get_property(memory, "reg", &len); if (!memcell_buf || len <= 0) continue; ranges = memory->n_addrs; new_range: /* these are order-sensitive, and modify the buffer pointer */ start = read_cell_ul(memory, &memcell_buf); size = read_cell_ul(memory, &memcell_buf); start = _ALIGN_DOWN(start, MEMORY_INCREMENT); size = _ALIGN_UP(size, MEMORY_INCREMENT); numa_domain = of_node_numa_domain(memory, depth); if (numa_domain >= MAX_NUMNODES) { if (numa_domain != 0xffff) printk(KERN_ERR "WARNING: memory at %lx maps " "to invalid NUMA node %d\n", start, numa_domain); numa_domain = 0; } node_set_online(numa_domain); if (max_domain < numa_domain) max_domain = numa_domain; /* * For backwards compatibility, OF splits the first node * into two regions (the first being 0-4GB). Check for * this simple case and complain if there is a gap in * memory */ if (node_data[numa_domain].node_spanned_pages) { unsigned long shouldstart = node_data[numa_domain].node_start_pfn + node_data[numa_domain].node_spanned_pages; if (shouldstart != (start / PAGE_SIZE)) { printk(KERN_ERR "Hole in node, disabling " "region start %lx length %lx\n", start, size); continue; } node_data[numa_domain].node_spanned_pages += size / PAGE_SIZE; } else { node_data[numa_domain].node_start_pfn = start / PAGE_SIZE; node_data[numa_domain].node_spanned_pages = size / PAGE_SIZE; } for (i = start ; i < (start+size); i += MEMORY_INCREMENT) numa_memory_lookup_table[i >> MEMORY_INCREMENT_SHIFT] = numa_domain; dbg("memory region %lx to %lx maps to domain %d\n", start, start+size, numa_domain); ranges--; if (ranges) goto new_range; } numnodes = max_domain + 1; return 0; }
int smu_init (void) { struct device_node *np; u32 *data; np = of_find_node_by_type(NULL, "smu"); if (np == NULL) return -ENODEV; if (smu_cmdbuf_abs == 0) { printk(KERN_ERR "SMU: Command buffer not allocated !\n"); return -EINVAL; } smu = alloc_bootmem(sizeof(struct smu_device)); if (smu == NULL) return -ENOMEM; memset(smu, 0, sizeof(*smu)); spin_lock_init(&smu->lock); smu->of_node = np; /* smu_cmdbuf_abs is in the low 2G of RAM, can be converted to a * 32 bits value safely */ smu->cmd_buf_abs = (u32)smu_cmdbuf_abs; smu->cmd_buf = (struct smu_cmd_buf *)abs_to_virt(smu_cmdbuf_abs); np = of_find_node_by_name(NULL, "smu-doorbell"); if (np == NULL) { printk(KERN_ERR "SMU: Can't find doorbell GPIO !\n"); goto fail; } data = (u32 *)get_property(np, "reg", NULL); of_node_put(np); if (data == NULL) { printk(KERN_ERR "SMU: Can't find doorbell GPIO address !\n"); goto fail; } /* Current setup has one doorbell GPIO that does both doorbell * and ack. GPIOs are at 0x50, best would be to find that out * in the device-tree though. */ smu->db_req = 0x50 + *data; smu->db_ack = 0x50 + *data; /* Doorbell buffer is currently hard-coded, I didn't find a proper * device-tree entry giving the address. Best would probably to use * an offset for K2 base though, but let's do it that way for now. */ smu->db_buf = ioremap(0x8000860c, 0x1000); if (smu->db_buf == NULL) { printk(KERN_ERR "SMU: Can't map doorbell buffer pointer !\n"); goto fail; } sys_ctrler = SYS_CTRLER_SMU; return 0; fail: smu = NULL; return -ENXIO; }
void __init htab_initialize(void) { unsigned long table; unsigned long pteg_count; unsigned long mode_rw; unsigned long base = 0, size = 0; int i; extern unsigned long tce_alloc_start, tce_alloc_end; DBG(" -> htab_initialize()\n"); /* Initialize page sizes */ htab_init_page_sizes(); /* * Calculate the required size of the htab. We want the number of * PTEGs to equal one half the number of real pages. */ htab_size_bytes = htab_get_table_size(); pteg_count = htab_size_bytes >> 7; htab_hash_mask = pteg_count - 1; if (firmware_has_feature(FW_FEATURE_LPAR)) { /* Using a hypervisor which owns the htab */ htab_address = NULL; _SDR1 = 0; } else { /* Find storage for the HPT. Must be contiguous in * the absolute address space. */ table = lmb_alloc(htab_size_bytes, htab_size_bytes); DBG("Hash table allocated at %lx, size: %lx\n", table, htab_size_bytes); htab_address = abs_to_virt(table); /* htab absolute addr + encoded htabsize */ _SDR1 = table + __ilog2(pteg_count) - 11; /* Initialize the HPT with no entries */ memset((void *)table, 0, htab_size_bytes); /* Set SDR1 */ mtspr(SPRN_SDR1, _SDR1); } mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX; /* On U3 based machines, we need to reserve the DART area and * _NOT_ map it to avoid cache paradoxes as it's remapped non * cacheable later on */ /* create bolted the linear mapping in the hash table */ for (i=0; i < lmb.memory.cnt; i++) { base = (unsigned long)__va(lmb.memory.region[i].base); size = lmb.memory.region[i].size; DBG("creating mapping for region: %lx : %lx\n", base, size); #ifdef CONFIG_U3_DART /* Do not map the DART space. Fortunately, it will be aligned * in such a way that it will not cross two lmb regions and * will fit within a single 16Mb page. * The DART space is assumed to be a full 16Mb region even if * we only use 2Mb of that space. We will use more of it later * for AGP GART. We have to use a full 16Mb large page. */ DBG("DART base: %lx\n", dart_tablebase); if (dart_tablebase != 0 && dart_tablebase >= base && dart_tablebase < (base + size)) { unsigned long dart_table_end = dart_tablebase + 16 * MB; if (base != dart_tablebase) BUG_ON(htab_bolt_mapping(base, dart_tablebase, __pa(base), mode_rw, mmu_linear_psize)); if ((base + size) > dart_table_end) BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, base + size, __pa(dart_table_end), mode_rw, mmu_linear_psize)); continue; } #endif /* CONFIG_U3_DART */ BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), mode_rw, mmu_linear_psize)); } /* * If we have a memory_limit and we've allocated TCEs then we need to * explicitly map the TCE area at the top of RAM. We also cope with the * case that the TCEs start below memory_limit. * tce_alloc_start/end are 16MB aligned so the mapping should work * for either 4K or 16MB pages. */ if (tce_alloc_start) { tce_alloc_start = (unsigned long)__va(tce_alloc_start); tce_alloc_end = (unsigned long)__va(tce_alloc_end); if (base + size >= tce_alloc_start) tce_alloc_start = base + size + 1; BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, __pa(tce_alloc_start), mode_rw, mmu_linear_psize)); } htab_finish_init(); DBG(" <- htab_initialize()\n"); }