/*
* variable value change call back routine
*/
int var_prt_vclchg(p_vc_record vcp)
{
/* unsigned long long now, chgtim; */
int otyp, ltime, htime;
handle net;
char s1[1024], s2[1024], s3[1024];
/* current time */
ltime = tf_getlongsimtime(&htime);
/* --
now = ((unsigned long long) ((unsigned long) htime)) << 32
| ((unsigned long long) ((unsigned long) ltime));
-* vc record time *-
chgtim = ((unsigned long long) ((unsigned long) vcp->vc_hightime)) << 32
| ((unsigned long long) ((unsigned long) vcp->vc_lowtime));
-- */
/* net handle assigned to user data field */
net = (handle) vcp->user_data;
otyp = acc_fetch_type(net);
if (vcp->vc_reason != event_value_change)
{
/* these do not have value, i.e. get va8ue return NULL with error */
if (otyp == accPort || otyp == accPortBit || otyp == accTerminal)
{
sprintf(s1, "obj=%s", acc_fetch_type_str(otyp));
}
else strcpy(s1, acc_fetch_value(net, "%b", NULL));
}
switch (vcp->vc_reason) {
case logic_value_change:
sprintf(s2, "scalar=%u(%s)", (unsigned) vcp->out_value.logic_value, s1);
break;
case sregister_value_change:
sprintf(s2, "sr-scalar=%u(%s)", (unsigned) vcp->out_value.logic_value, s1);
break;
case real_value_change: case realtime_value_change:
sprintf(s2, "**error**");
break;
case event_value_change:
strcpy(s2, "**event**");
break;
default:
sprintf(s2, "vector=%s", s1);
}
/* --
io_printf("--> now %uL (chg time %uL): %s=%s\n", now, chgtim,
-- */
if (otyp != accTerminal) strcpy(s3, acc_fetch_fullname(net));
else strcpy(s3, "**terminal**");
io_printf("--> now %d (chg time %d): %s=%s\n", ltime, vcp->vc_lowtime, s3,
s2);
return(0);
}
/*
* routine to add vcl to one net/reg/var/event
*/
static void add_vcl(handle net)
{
int typ, fulltyp;
char s1[1024];
/* DBG remove -- */
typ = acc_fetch_type(net);
fulltyp = acc_fetch_fulltype(net);
if (typ != accTerminal) strcpy(s1, acc_fetch_fullname(net));
else strcpy(s1, "**terminal**");
io_printf("Adding vcl for %s type %s (fulltype %s)\n", s1,
acc_fetch_type_str(typ), acc_fetch_type_str(fulltyp));
/* --- */
if (typ == accNet)
{
acc_vcl_add(net, wire_prt_vclchg, (void *) net, vcl_verilog_strength);
}
else acc_vcl_add(net, var_prt_vclchg, (void *) net, vcl_verilog_logic);
}
FliIterator::FliIterator(GpiImplInterface *impl, GpiObjHdl *hdl) : GpiIterator(impl, hdl),
m_vars(),
m_sigs(),
m_regs(),
m_currentHandles(NULL)
{
FliObj *fli_obj = dynamic_cast<FliObj *>(m_parent);
int type = fli_obj->get_acc_full_type();
LOG_DEBUG("fli_iterator::Create iterator for %s of type %d:%s", m_parent->get_fullname().c_str(), type, acc_fetch_type_str(type));
if (NULL == (selected = iterate_over.get_options(type))) {
LOG_WARN("FLI: Implementation does not know how to iterate over %s(%d)",
acc_fetch_type_str(type), type);
return;
}
/* Find the first mapping type that yields a valid iterator */
for (one2many = selected->begin(); one2many != selected->end(); one2many++) {
/* GPI_GENARRAY are pseudo-regions and all that should be searched for are the sub-regions */
if (m_parent->get_type() == GPI_GENARRAY && *one2many != FliIterator::OTM_REGIONS) {
LOG_DEBUG("fli_iterator OneToMany=%d skipped for GPI_GENARRAY type", *one2many);
continue;
}
populate_handle_list(*one2many);
switch (*one2many) {
case FliIterator::OTM_CONSTANTS:
case FliIterator::OTM_VARIABLE_SUB_ELEMENTS:
m_currentHandles = &m_vars;
m_iterator = m_vars.begin();
break;
case FliIterator::OTM_SIGNALS:
case FliIterator::OTM_SIGNAL_SUB_ELEMENTS:
m_currentHandles = &m_sigs;
m_iterator = m_sigs.begin();
break;
case FliIterator::OTM_REGIONS:
m_currentHandles = &m_regs;
m_iterator = m_regs.begin();
break;
default:
LOG_WARN("Unhandled OneToMany Type (%d)", *one2many);
}
if (m_iterator != m_currentHandles->end())
break;
LOG_DEBUG("fli_iterator OneToMany=%d returned NULL", *one2many);
}
if (m_iterator == m_currentHandles->end()) {
LOG_DEBUG("fli_iterator return NULL for all relationships on %s (%d) kind:%s",
m_parent->get_name_str(), type, acc_fetch_type_str(type));
selected = NULL;
return;
}
LOG_DEBUG("Created iterator working from scope %d",
*one2many);
}
