static void vexpress_ax_devices_init(void)
{
add_cfi_flash_device(0, 0x08000000, SZ_64M, 0);
add_cfi_flash_device(1, 0x0c000000, SZ_64M, 0);
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x1a000000,
64 * 1024, IORESOURCE_MEM, NULL);
armlinux_set_bootparams((void *)(0x80000100));
}
static void vexpress_a9_legacy_devices_init(void)
{
add_cfi_flash_device(0, 0x40000000, SZ_64M, 0);
add_cfi_flash_device(1, 0x44000000, SZ_64M, 0);
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x4e000000,
64 * 1024, IORESOURCE_MEM, NULL);
armlinux_set_architecture(MACH_TYPE_VEXPRESS);
armlinux_set_bootparams((void *)(0x60000100));
}
static int scb9328_devices_init(void)
{
int i;
imx_gpio_mode(PA23_PF_CS5);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 21);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 22);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 23);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 24);
for (i = 0; i < ARRAY_SIZE(leds); i++)
led_gpio_register(&leds[i]);
/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR);
imx1_setup_eimcs(0, 0x000F2000, 0x11110d01);
imx1_setup_eimcs(1, 0x000F0a00, 0x11110601);
imx1_setup_eimcs(3, 0x000FFFFF, 0x00000303);
imx1_setup_eimcs(4, 0x000F0a00, 0x11110301);
imx1_setup_eimcs(5, 0x00008400, 0x00000D03);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x10000000, 16 * 1024 * 1024, 0);
add_dm9000_device(DEVICE_ID_DYNAMIC, 0x16000000, 0x16000004,
IORESOURCE_MEM_16BIT, &dm9000_data);
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0x08000100);
armlinux_set_architecture(MACH_TYPE_SCB9328);
return 0;
}
static int devices_init (void)
{
struct stat s;
int ret;
/*
* Flash can be 16MB or 32MB, setup for the last 32MB no matter
* what we find later.
*/
mpc5200_setup_cs(MPC5200_BOOTCS, 0xfe000000, SZ_32M, 0x0008fd00);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xfe000000, 32 * 1024 * 1024, 0);
add_generic_device("fec_mpc5xxx", DEVICE_ID_DYNAMIC, NULL, MPC5XXX_FEC, 0x200,
IORESOURCE_MEM, &fec_info);
i2c_register_board_info(0, pcm030_i2c_devices, ARRAY_SIZE(pcm030_i2c_devices));
add_generic_device("i2c-fsl", DEVICE_ID_DYNAMIC, NULL, MPC5XXX_I2C2, 0x100,
IORESOURCE_MEM, &pcm030_i2c_plat);
ret = stat("/dev/nor0", &s);
if (ret)
return 0;
devfs_add_partition("nor0", s.st_size - SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", s.st_size - SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
static int clps711x_devices_init(void)
{
u32 serial_h = 0, serial_l = readl(UNIQID);
void *cfi_io;
/* Setup Chipselects */
clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8);
clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 |
MEMCFG_CLKENB);
clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_32);
cfi_io = map_io_sections(CS0_BASE, (void *)0x90000000, SZ_32M);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M,
IORESOURCE_MEM);
devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED,
"self0");
devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED,
"env0");
armlinux_set_architecture(MACH_TYPE_CLEP7212);
armlinux_set_serial(((u64)serial_h << 32) | serial_l);
return 0;
}
static int ep93xx_devices_init(void)
{
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0);
/*
* Create partitions that should be
* not touched by any regular user
*/
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 6, data width is 16 bit
*/
add_generic_device("ep93xx_eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM,
NULL);
armlinux_set_bootparams((void *)CONFIG_EP93XX_SDRAM_BANK0_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE);
return 0;
}
static int at91rm9200ek_devices_init(void)
{
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
at91_set_gpio_output(AT91_PIN_PA23, 1);
at91_add_device_eth(0, ðer_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, SZ_8M, 0);
/* USB Host */
at91_add_device_usbh_ohci(&ek_usbh_data);
ek_device_add_leds();
ek_add_device_udc();
ek_add_device_spi();
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
#endif
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_AT91RM9200EK);
return 0;
}
static int pcm043_devices_init(void)
{
uint32_t reg;
char *envstr;
unsigned long bbu_nand_flags = 0;
/* CS0: Nor Flash */
imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900);
led_gpio_register(&led0);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
imx35_add_fec(&fec_info);
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envstr = "NAND";
bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT;
break;
case BOOTSOURCE_NOR:
default:
devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
envstr = "NOR";
break;
}
pr_info("using environment from %s flash\n", envstr);
imx35_add_fb(&ipu_fb_data);
armlinux_set_architecture(MACH_TYPE_PCM043);
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
bbu_nand_flags);
return 0;
}
static int malta_devices_init(void)
{
add_cfi_flash_device(0, 0x1e000000, SZ_4M, 0);
devfs_add_partition("nor0", 0x0, SZ_512K, DEVFS_PARTITION_FIXED, "self");
devfs_add_partition("nor0", SZ_512K, SZ_64K, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
static int lubbock_devices_init(void)
{
void *nor0_iospace;
armlinux_set_architecture(MACH_TYPE_LUBBOCK);
pxa_add_uart((void *)0x40100000, 0);
pxa_add_pwm((void *)0x40b00000, 0);
nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M);
add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0);
add_cfi_flash_device(1, 0x04000000, SZ_64M, 0);
devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED,
"env0");
add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL,
0x0c000300, 0xff4000, IORESOURCE_MEM,
&smsc91x_pdata);
return 0;
}
static int pcm037_devices_init(void)
{
/* CS0: Nor Flash */
imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
/* CS1: Network Controller */
imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302);
/* CS4: SRAM */
imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00);
/* CS5: SJA1000 */
imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
imx31_add_mmc0(NULL);
/*
* Create partitions that should be
* not touched by any regular user
*/
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
/*
* up to 2MiB static RAM type memory, connected
* to CS4, data width is 16 bit
*/
add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */
IORESOURCE_MEM_WRITEABLE);
imx31_add_nand(&nand_info);
/*
* SMSC 9217 network controller
* connected to CS line 1 and interrupt line
* GPIO3, data width is 16 bit
*/
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR,
MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata);
#ifdef CONFIG_USB
pcm037_usb_init();
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL);
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL);
#endif
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_PCM037);
return 0;
}
static int mx21ads_devices_init(void)
{
int i;
unsigned int mode[] = {
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
};
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR,
32 * 1024 * 1024, 0);
imx21_add_nand(&nand_info);
add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
MX21_CS1_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
imx21_add_fb(&imx_fb_data);
armlinux_set_bootparams((void *)0xc0000100);
armlinux_set_architecture(MACH_TYPE_MX21ADS);
return 0;
}
static int f3s_devices_init(void)
{
uint32_t reg;
/* CS0: Nor Flash */
imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
case 0x00: /* NOR is the source */
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
break;
}
set_silicon_rev(imx_silicon_revision());
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx35_add_i2c0(NULL);
imx35_add_fec(&fec_info);
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
IORESOURCE_MEM, NULL);
imx35_add_mmc0(NULL);
imx35_add_fb(&ipu_fb_data);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX35_3DS);
return 0;
}
static int virt_env_init(void)
{
add_cfi_flash_device(0, 0x00000000, SZ_128M, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
defaultenv_append_directory(defaultenv_qemu_virt64);
return 0;
}
static int vpb_devices_init(void)
{
add_cfi_flash_device(-1, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
add_generic_device("smc91c111", -1, NULL, VERSATILE_ETH_BASE, 64 * 1024,
IORESOURCE_MEM, NULL);
armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
armlinux_set_bootparams((void *)(0x00000100));
return 0;
}
static int p1010rdb_devices_init(void)
{
add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 32 << 20, 0);
devfs_add_partition("nor0", 0x1f80000, 0x80000, DEVFS_PARTITION_FIXED,
"self0");
devfs_add_partition("nor0", 0x1f60000, 0x10000, DEVFS_PARTITION_FIXED,
"env0");
add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100,
IORESOURCE_MEM, &i2cplat[0]);
add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100,
IORESOURCE_MEM, &i2cplat[1]);
board_eth_init();
return 0;
}
static int da923rc_devices_init(void)
{
add_cfi_flash_device(0, 0xfe000000, 32 << 20, 0);
devfs_add_partition("nor0", 0x0, 0x8000, DEVFS_PARTITION_FIXED, "env0");
devfs_add_partition("nor0", 0x1f80000, 8 << 16, DEVFS_PARTITION_FIXED,
"self0");
add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100,
IORESOURCE_MEM, &i2cplat[0]);
add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100,
IORESOURCE_MEM, &i2cplat[1]);
board_eth_init();
return 0;
}
static int devices_init(void)
{
add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0);
add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR,
0x100, IORESOURCE_MEM, &i2cplat);
add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
0x100, IORESOURCE_MEM, &i2cplat);
fsl_eth_init(2, &gfar_info[0]);
fsl_eth_init(3, &gfar_info[1]);
devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
"self0");
return 0;
}
static int pm9263_devices_init(void)
{
at91_set_gpio_input(w1_pdata.pin, 0);
add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata);
pm_add_device_nand();
pm9263_add_device_eth();
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x10000, DEVFS_PARTITION_FIXED, "env0");
armlinux_set_architecture(MACH_TYPE_PM9263);
return 0;
}
static int netx_devices_init(void) {
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, ð0_data);
add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, ð1_data);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
/* Do not overwrite primary env for now */
devfs_add_partition("nor0", 0xc0000, 0x80000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_NXDB500);
return 0;
}
static int mx27ads_devices_init(void)
{
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
};
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_fec(&fec_info);
devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_MX27ADS);
return 0;
}
static int pcm027_devices_init(void)
{
void *cfi_iospace;
add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x14000300, 16,
IORESOURCE_MEM, NULL);
cfi_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_32M);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_iospace, SZ_32M, 0);
pxa_add_fb((void *)0x44000000, &fb_pdata);
armlinux_set_architecture(MACH_TYPE_PCM027);
devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
return 0;
}
static int mmccpu_devices_init(void)
{
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
at91_add_device_eth(&macb_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_MMCCPU);
return 0;
}
static int at91sam9263ek_devices_init(void)
{
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
ek_add_device_nand();
at91_add_device_eth(0, &macb_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 8 * 1024 * 1024, 0);
ek_add_device_mci();
ek_device_add_leds();
ek_add_device_udc();
ek_add_device_buttons();
if (IS_ENABLED(CONFIG_DRIVER_CFI) && cdev_by_name("nor0")) {
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
} else if (IS_ENABLED(CONFIG_NAND_ATMEL)) {
devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
}
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_AT91SAM9263EK);
return 0;
}
static int devices_init (void)
{
struct stat s;
int ret;
/*
* Flash can be 16MB or 32MB, setup for the last 32MB no matter
* what we find later.
*/
mpc5200_setup_cs(MPC5200_BOOTCS, 0xfe000000, SZ_32M, 0x0008fd00);
add_cfi_flash_device(-1, 0xfe000000, 32 * 1024 * 1024, 0);
add_generic_device("fec_mpc5xxx", -1, NULL, MPC5XXX_FEC, 0x200,
IORESOURCE_MEM, &fec_info);
ret = stat("/dev/nor0", &s);
if (ret)
return 0;
devfs_add_partition("nor0", s.st_size - SZ_1M, SZ_512K, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", s.st_size - SZ_512K, SZ_512K, PARTITION_FIXED, "env0");
return 0;
}
static int pcm038_devices_init(void)
{
int i;
u64 uid = 0;
char *envdev;
long sram_size;
unsigned int mode[] = {
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT,
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* CSPI1 */
PD25_PF_CSPI1_RDY,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT,
#ifdef CONFIG_MACH_PCM970_BASEBOARD
PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT,
#endif
/* Display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB OTG */
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* I2C1 */
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
};
/* configure 16 bit nor flash on cs0 */
imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900);
/* configure SRAM on cs1 */
imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
/* SRAM can be up to 2MiB */
sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M);
if (sram_size)
add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size,
IORESOURCE_MEM_WRITEABLE);
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
pcm038_power_init();
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
gpio_set_value(PCM038_GPIO_FEC_RST, 1);
imx27_add_fec(&fec_info);
/* Apply delay for STP line to stop ULPI */
gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
mdelay(1);
imx_gpio_mode(PE1_PF_USBOTG_STP);
imx27_add_usbotg(&pcm038_otg_pdata);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_add_partition("nand0", 0, SZ_512K,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0, SZ_512K,
DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
}
pr_notice("Using environment in %s Flash\n", envdev);
if (imx_iim_read(1, 0, &uid, 6) == 6)
armlinux_set_serial(uid);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}
static int eukrea_cpuimx27_devices_init(void)
{
char *envdev = "no";
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
#ifdef CONFIG_DRIVER_SERIAL_IMX
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
#endif
#ifdef CONFIG_DRIVER_VIDEO_IMX
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT,
GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT,
#endif
};
/* configure 16 bit nor flash on cs0 */
CS0U = 0x00008F03;
CS0L = 0xA0330D01;
CS0A = 0x002208C0;
/* initialize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
add_cfi_flash_device(-1, 0xC2000000, 32 * 1024 * 1024, 0);
#endif
imx27_add_nand(&nand_info);
PCCR0 |= PCCR0_I2C1_EN;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx27_add_i2c0(NULL);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
printf("Using environment in %s Flash\n", envdev);
#ifdef CONFIG_DRIVER_VIDEO_IMX
imx_add_fb((void *)0x10021000, &eukrea_cpuimx27_fb_data);
gpio_direction_output(GPIO_PORTE | 5, 0);
gpio_set_value(GPIO_PORTE | 5, 1);
gpio_direction_output(GPIO_PORTA | 25, 0);
gpio_set_value(GPIO_PORTA | 25, 1);
#endif
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX27);
return 0;
}
static int pcm038_devices_init(void)
{
int i;
char *envdev;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
PD25_PF_CSPI1_RDY,
GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
/* I2C1 */
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
};
/* configure 16 bit nor flash on cs0 */
CS0U = 0x22C2CF00;
CS0L = 0x75000D01;
CS0A = 0x00000900;
/* configure SRAM on cs1 */
CS1U = 0x0000d843;
CS1L = 0x22252521;
CS1A = 0x22220a00;
/* configure SJA1000 on cs4 */
CS4U = 0x0000DCF6;
CS4L = 0x444A0301;
CS4A = 0x44443302;
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
PCCR0 |= PCCR0_CSPI1_EN;
PCCR1 |= PCCR1_PERCLK2_EN;
gpio_direction_output(GPIO_PORTD | 28, 0);
gpio_set_value(GPIO_PORTD | 28, 0);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN;
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
#ifdef CONFIG_USB
pcm038_usbh_init();
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
imx27_add_fec(&fec_info);
switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
case GPCR_BOOT_8BIT_NAND_2k:
case GPCR_BOOT_16BIT_NAND_2k:
case GPCR_BOOT_16BIT_NAND_512:
case GPCR_BOOT_8BIT_NAND_512:
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
}
printf("Using environment in %s Flash\n", envdev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}
