/*------------------------------------------------------------------------
* (function: connect_nodes)
* Connect one output node to the inputs of the input node
*----------------------------------------------------------------------*/
void connect_nodes(nnode_t *out_node, int out_idx, nnode_t *in_node, int in_idx)
{
npin_t *new_in_pin;
oassert(out_node->num_output_pins > out_idx);
oassert(in_node->num_input_pins > in_idx);
new_in_pin = allocate_npin();
/* create the pin that hooks up to the input */
add_input_pin_to_node(in_node, new_in_pin, in_idx);
if (out_node->output_pins[out_idx] == NULL)
{
/* IF - this node has no output net or pin */
npin_t *new_out_pin;
nnet_t *new_net;
new_net = allocate_nnet();
new_out_pin = allocate_npin();
/* create the pin that hooks up to the input */
add_output_pin_to_node(out_node, new_out_pin, out_idx);
/* hook up in pin out of the new net */
add_fanout_pin_to_net(new_net, new_in_pin);
/* hook up the new pin 2 to this new net */
add_driver_pin_to_net(new_net, new_out_pin);
}
else
{
/* ELSE - there is a net so we just add a fanout */
/* hook up in pin out of the new net */
add_fanout_pin_to_net(out_node->output_pins[out_idx]->net, new_in_pin);
}
}
/*---------------------------------------------------------------------------------------------
* (function: make_not_gate_with_input)
* Creates a not gate and attaches it to the inputs
*-------------------------------------------------------------------------------------------*/
nnode_t *make_not_gate_with_input(npin_t *input_pin, nnode_t *node, short mark)
{
nnode_t *logic_node;
logic_node = make_not_gate(node, mark);
/* add the input ports as needed */
add_input_pin_to_node(logic_node, input_pin, 0);
return logic_node;
}
/*---------------------------------------------------------------------------
* (function: hookup_hb_input_pins_from_signal_list)
* For each pin in this list hook it up to the inputs according to
* indexes and width. Extra pins are tied to PAD for later resolution.
*--------------------------------------------------------------------------*/
void hookup_hb_input_pins_from_signal_list(nnode_t *node, int n_start_idx, signal_list_t* input_list, int il_start_idx, int width, netlist_t *netlist)
{
int i;
for (i = 0; i < width; i++)
{
if (il_start_idx+i < input_list->count)
{
oassert(input_list->count > (il_start_idx+i));
add_input_pin_to_node(node, input_list->pins[il_start_idx+i], n_start_idx+i);
}
else
{
/* connect with "pad" signal for later resolution */
add_input_pin_to_node(node, get_pad_pin(netlist), n_start_idx+i);
if (global_args.all_warnings)
warning_message(NETLIST_ERROR, -1, -1, "padding an input port with HB_PAD for node %s\n", node->name);
}
}
}
/*---------------------------------------------------------------------------
* (function: hookup_input_pins_from_signal_list)
* For each pin in this list hook it up to the inputs according to indexes and width
*--------------------------------------------------------------------------*/
void hookup_input_pins_from_signal_list(nnode_t *node, int n_start_idx, signal_list_t* input_list, int il_start_idx, int width, netlist_t *netlist)
{
int i;
for (i = 0; i < width; i++)
{
if (il_start_idx+i < input_list->count)
{
oassert(input_list->count > (il_start_idx+i));
npin_t *pin = input_list->pins[il_start_idx+i];
add_input_pin_to_node(node, pin, n_start_idx+i);
}
else
{
/* pad with 0's */
add_input_pin_to_node(node, get_zero_pin(netlist), n_start_idx+i);
if (global_args.all_warnings)
warning_message(NETLIST_ERROR, -1, -1, "padding an input port with 0 for node %s\n", node->name);
}
}
}
/*---------------------------------------------------------------------------------------------
* (function: make_1port_logic_gate_with_inputs)
* Make a gate with variable sized inputs, 1 output, and connect to the supplied inputs
*-------------------------------------------------------------------------------------------*/
nnode_t *make_1port_logic_gate_with_inputs(operation_list type, int width, signal_list_t *pin_list, nnode_t *node, short mark)
{
nnode_t *logic_node;
int i;
logic_node = make_1port_gate(type, width, 1, node, mark);
/* hookup all the pins */
for (i = 0; i < width; i++)
{
add_input_pin_to_node(logic_node, pin_list->pins[i], i);
}
return logic_node;
}
/*-------------------------------------------------------------------------
* (function: remap_pin_to_new_node)
*-----------------------------------------------------------------------*/
void remap_pin_to_new_node(npin_t *pin, nnode_t *new_node, int pin_idx)
{
if (pin->type == INPUT) {
/* clean out the entry in the old net */
pin->node->input_pins[pin->pin_node_idx] = NULL;
/* do the new addition */
add_input_pin_to_node(new_node, pin, pin_idx);
}
else if (pin->type == OUTPUT) {
/* clean out the entry in the old net */
pin->node->output_pins[pin->pin_node_idx] = NULL;
/* do the new addition */
add_output_pin_to_node(new_node, pin, pin_idx);
}
}
/*-------------------------------------------------------------------------
* (function: pad_multiplier)
*
* Fill out a multiplier to a fixed size. Size is retrieved from global
* hard_multipliers data.
*
* NOTE: The inputs are extended based on multiplier padding setting.
*-----------------------------------------------------------------------*/
void pad_multiplier(nnode_t *node, netlist_t *netlist)
{
int diffa, diffb, diffout, i;
int sizea, sizeb, sizeout;
int ina, inb;
int testa, testb;
static int pad_pin_number = 0;
oassert(node->type == MULTIPLY);
oassert(hard_multipliers != NULL);
sizea = node->input_port_sizes[0];
sizeb = node->input_port_sizes[1];
sizeout = node->output_port_sizes[0];
record_mult_distribution(node);
/* Calculate the BEST fit hard multiplier to use */
ina = hard_multipliers->inputs->size;
inb = hard_multipliers->inputs->next->size;
if (ina < inb)
{
ina = hard_multipliers->inputs->next->size;
inb = hard_multipliers->inputs->size;
}
diffa = ina - sizea;
diffb = inb - sizeb;
diffout = hard_multipliers->outputs->size - sizeout;
if (configuration.split_hard_multiplier == 1)
{
struct s_linked_vptr *plist = hard_multipliers->pb_types;
while ((diffa + diffb) && plist)
{
t_pb_type *physical = (t_pb_type *)(plist->data_vptr);
plist = plist->next;
testa = physical->ports[0].num_pins;
testb = physical->ports[1].num_pins;
if ((testa >= sizea) && (testb >= sizeb) &&
((testa - sizea + testb - sizeb) < (diffa + diffb)))
{
diffa = testa - sizea;
diffb = testb - sizeb;
diffout = physical->ports[2].num_pins - sizeout;
}
}
}
/* Expand the inputs */
if ((diffa != 0) || (diffb != 0))
{
allocate_more_input_pins(node, diffa + diffb);
/* Shift pins for expansion of first input pins */
if (diffa != 0)
{
for (i = 1; i <= sizeb; i++)
{
move_input_pin(node, sizea + sizeb - i, node->num_input_pins - diffb - i);
}
/* Connect unused first input pins to zero/pad pin */
for (i = 0; i < diffa; i++)
{
if (configuration.mult_padding == 0)
add_input_pin_to_node(node, get_zero_pin(netlist), i + sizea);
else
add_input_pin_to_node(node, get_pad_pin(netlist), i + sizea);
}
node->input_port_sizes[0] = sizea + diffa;
}
if (diffb != 0)
{
/* Connect unused second input pins to zero/pad pin */
for (i = 1; i <= diffb; i++)
{
if (configuration.mult_padding == 0)
add_input_pin_to_node(node, get_zero_pin(netlist), node->num_input_pins - i);
else
add_input_pin_to_node(node, get_pad_pin(netlist), node->num_input_pins - i);
}
node->input_port_sizes[1] = sizeb + diffb;
}
}
/* Expand the outputs */
if (diffout != 0)
{
allocate_more_output_pins(node, diffout);
for (i = 0; i < diffout; i++)
{
// Add new pins to the higher order spots.
npin_t *new_pin = allocate_npin();
// Pad outputs with a unique and descriptive name to avoid collisions.
new_pin->name = append_string("", "unconnected_multiplier_output~%d", pad_pin_number++);
add_output_pin_to_node(node, new_pin, i + sizeout);
}
node->output_port_sizes[0] = sizeout + diffout;
}
return;
}
/*---------------------------------------------------------------------------
* (function: instantiate_simple_soft_multiplier )
* Sample 4x4 multiplier to help understand logic.
*
* a3 a2 a1 a0
* b3 b2 b1 b0
* ---------------------------
* c03 c02 c01 c00
* + c13 c12 c11 c10
* -----------------------------------
* r14 r13 r12 r11 r10
* + c23 c22 c21 c20
* -----------------------------------
* r24 r23 r22 r21 r20
* + c33 c32 c31 c30
* ------------------------------------
* o7 o6 o5 o4 o3 o2 o1 o0
*
* In the first case will be c01
*-------------------------------------------------------------------------*/
void instantiate_simple_soft_multiplier(nnode_t *node, short mark, netlist_t *netlist)
{
int width_a;
int width_b;
int width;
int multiplier_width;
int multiplicand_width;
nnode_t **adders_for_partial_products;
nnode_t ***partial_products;
int multiplicand_offset_index;
int multiplier_offset_index;
int current_index;
int i, j;
/* need for an carry-ripple-adder for each of the bits of port B. */
/* good question of which is better to put on the bottom of multiplier. Larger means more smaller adds, or small is
* less large adds */
oassert(node->num_output_pins > 0);
oassert(node->num_input_pins > 0);
oassert(node->num_input_port_sizes == 2);
oassert(node->num_output_port_sizes == 1);
width_a = node->input_port_sizes[0];
width_b = node->input_port_sizes[1];
width = node->output_port_sizes[0];
multiplicand_width = width_b;
multiplier_width = width_a;
/* offset is related to which multport is chosen as the multiplicand */
multiplicand_offset_index = width_a;
multiplier_offset_index = 0;
adders_for_partial_products = (nnode_t**)malloc(sizeof(nnode_t*)*multiplicand_width-1);
/* need to generate partial products for each bit in width B. */
partial_products = (nnode_t***)malloc(sizeof(nnode_t**)*multiplicand_width);
/* generate the AND partial products */
for (i = 0; i < multiplicand_width; i++)
{
/* create the memory for each AND gate needed for the levels of partial products */
partial_products[i] = (nnode_t**)malloc(sizeof(nnode_t*)*multiplier_width);
if (i < multiplicand_width - 1)
{
adders_for_partial_products[i] = make_2port_gate(ADD, multiplier_width+1, multiplier_width+1, multiplier_width+1, node, mark);
}
for (j = 0; j < multiplier_width; j++)
{
/* create each one of the partial products */
partial_products[i][j] = make_1port_logic_gate(LOGICAL_AND, 2, node, mark);
}
}
/* generate the coneections to the AND gates */
for (i = 0; i < multiplicand_width; i++)
{
for (j = 0; j < multiplier_width; j++)
{
/* hookup the input of B to each AND gate */
if (j == 0)
{
/* IF - this is the first time we are mapping multiplicand port then can remap */
remap_pin_to_new_node(node->input_pins[i+multiplicand_offset_index], partial_products[i][j], 0);
}
else
{
/* ELSE - this needs to be a new ouput of the multiplicand port */
add_input_pin_to_node(partial_products[i][j], copy_input_npin(partial_products[i][0]->input_pins[0]), 0);
}
/* hookup the input of the multiplier to each AND gate */
if (i == 0)
{
/* IF - this is the first time we are mapping multiplier port then can remap */
remap_pin_to_new_node(node->input_pins[j+multiplier_offset_index], partial_products[i][j], 1);
}
else
{
/* ELSE - this needs to be a new ouput of the multiplier port */
add_input_pin_to_node(partial_products[i][j], copy_input_npin(partial_products[0][j]->input_pins[1]), 1);
}
}
}
/* hookup each of the adders */
for (i = 0; i < multiplicand_width-1; i++) // -1 since the first stage is a combo of partial products while all others are part of tree
{
for (j = 0; j < multiplier_width+1; j++) // +1 since adders are one greater than multwidth to pass carry
{
/* join to port 1 of the add one of the partial products. */
if (i == 0)
{
/* IF - this is the first addition row, then adding two sets of partial products and first set is from the c0* */
if (j < multiplier_width-1)
{
/* IF - we just take an element of the first list c[0][j+1]. */
connect_nodes(partial_products[i][j+1], 0, adders_for_partial_products[i], j);
}
else
{
/* ELSE - this is the last input to the first adder, then we pass in 0 since no carry yet */
add_input_pin_to_node(adders_for_partial_products[i], get_zero_pin(netlist), j);
}
}
else if (j < multiplier_width)
{
/* ELSE - this is the standard situation when we need to hookup this adder with a previous adder, r[i-1][j+1] */
connect_nodes(adders_for_partial_products[i-1], j+1, adders_for_partial_products[i], j);
}
else
{
add_input_pin_to_node(adders_for_partial_products[i], get_zero_pin(netlist), j);
}
if (j < multiplier_width)
{
/* IF - this is not most significant bit then just add current partial product */
connect_nodes(partial_products[i+1][j], 0, adders_for_partial_products[i], j+multiplier_width+1);
}
else
{
add_input_pin_to_node(adders_for_partial_products[i], get_zero_pin(netlist), j+multiplier_width+1);
}
}
}
current_index = 0;
/* hookup the outputs */
for (i = 0; i < width; i++)
{
if (multiplicand_width == 1)
{
// this is undealt with
error_message(1,-1,-1,"Cannot create soft multiplier with multiplicand width of 1.\n");
}
else if (i == 0)
{
/* IF - this is the LSbit, then we use a pass through from the partial product */
remap_pin_to_new_node(node->output_pins[i], partial_products[0][0], 0);
}
else if (i < multiplicand_width - 1)
{
/* ELSE IF - these are the middle values that come from the LSbit of partial adders */
remap_pin_to_new_node(node->output_pins[i], adders_for_partial_products[i-1], 0);
}
else
{
/* ELSE - the final outputs are straight from the outputs of the last adder */
remap_pin_to_new_node(node->output_pins[i], adders_for_partial_products[multiplicand_width-2], current_index);
current_index++;
}
}
/* soft map the adders if they need to be mapped */
for (i = 0; i < multiplicand_width - 1; i++)
{
instantiate_add_w_carry(adders_for_partial_products[i], mark, netlist);
}
/* Cleanup everything */
if (adders_for_partial_products != NULL)
{
free(adders_for_partial_products);
}
/* generate the AND partial products */
for (i = 0; i < multiplicand_width; i++)
{
/* create the memory for each AND gate needed for the levels of partial products */
if (partial_products[i] != NULL)
{
free(partial_products[i]);
}
}
if (partial_products != NULL)
{
free(partial_products);
}
}