static vsf_err_t nuc100swj_init_iap(void)
{
uint32_t reg;
uint8_t verify_buff[sizeof(iap_code)];
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt nuc100");
return ERRCODE_FAILURE_OPERATION;
}
// enable isp clock and ispen bit
reg = NUC100_REG_AHBCLK_ISPEN;
if (adi_memap_write_reg32(NUC100_REG_AHBCLK, ®, 0))
{
return VSFERR_FAIL;
}
reg = NUC100_REG_ISPCON_ISPFF | NUC100_REG_ISPCON_LDUEN |
NUC100_REG_ISPCON_CFGUEN | NUC100_REG_ISPCON_ISPEN;
if (adi_memap_write_reg32(NUC100_REG_ISPCON, ®, 1))
{
return VSFERR_FAIL;
}
// write iap_code
if (adi_memap_write_buf32(NUC100_IAP_BASE, (uint8_t*)iap_code,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap_code to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify iap_code
memset(verify_buff, 0, sizeof(iap_code));
if (adi_memap_read_buf32(NUC100_IAP_BASE, verify_buff,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, iap_code, sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
// write pc
reg = NUC100_IAP_BASE + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run iap");
return ERRCODE_FAILURE_OPERATION;
}
return VSFERR_NONE;
}
static vsf_err_t nuc400swj_iap_run(struct nuc400_fl_t *fl,
struct nuc400swj_iap_cmd_t * cmd)
{
uint32_t buff_tmp[6];
if (nuc400swj_iap_wait_param_taken(fl))
{
return VSFERR_FAIL;
}
memset(buff_tmp, 0, sizeof(buff_tmp));
buff_tmp[0] = NUC400_REG_FMC_BA;
buff_tmp[1] = cmd->tgt_addr;
buff_tmp[2] = cmd->src_addr;
buff_tmp[3] = cmd->command;
buff_tmp[4] = cmd->cnt;
buff_tmp[5] = 1; // sync
// write iap command with sync to target SRAM
// sync is 4-byte AFTER command in sram
if (adi_memap_write_buf32(NUC400_IAP_COMMAND_ADDR,
(uint8_t*)buff_tmp, sizeof(buff_tmp)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap cmd to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
fl->iap_cnt++;
fl->iap_busy = true;
return VSFERR_NONE;
}
static vsf_err_t nuc400swj_init_iap(void)
{
uint32_t reg;
uint8_t verify_buff[sizeof(iap_code)];
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt nuc400");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_unlock())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "unlock NUC chip");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_fmc_enable())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "enable FMC");
return ERRCODE_FAILURE_OPERATION;
}
// write iap_code
if (adi_memap_write_buf32(NUC400_IAP_BASE, (uint8_t*)iap_code,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap_code to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify iap_code
memset(verify_buff, 0, sizeof(iap_code));
if (adi_memap_read_buf32(NUC400_IAP_BASE, verify_buff,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, iap_code, sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
// write pc
reg = NUC400_IAP_BASE + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run iap");
return ERRCODE_FAILURE_OPERATION;
}
return VSFERR_NONE;
}
static vsf_err_t kinetisswj_iap_init(struct kinetis_fl_t *fl)
{
uint8_t verify_buff[sizeof(iap_code)];
uint32_t reg;
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt lpc1000");
return ERRCODE_FAILURE_OPERATION;
}
// write iap_code to target SRAM
if (adi_memap_write_buf32(KINETIS_IAP_BASE, (uint8_t*)iap_code,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap_code to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify iap_code
memset(verify_buff, 0, sizeof(iap_code));
if (adi_memap_read_buf32(KINETIS_IAP_BASE, verify_buff,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, iap_code, sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
// write pc
reg = KINETIS_IAP_BASE + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run iap");
return ERRCODE_FAILURE_OPERATION;
}
fl->iap_cnt = 0;
return VSFERR_NONE;
}
vsf_err_t stm32swj_fl_run(struct stm32_fl_t *fl, struct stm32_fl_cmd_t *cmd)
{
uint32_t buff_tmp[10];
buff_tmp[0] = SYS_TO_LE_U32(cmd->cr_addr);
buff_tmp[1] = SYS_TO_LE_U32(cmd->cr_value1);
buff_tmp[2] = SYS_TO_LE_U32(cmd->cr_value2);
buff_tmp[3] = SYS_TO_LE_U32(cmd->sr_addr);
buff_tmp[4] = SYS_TO_LE_U32(cmd->sr_busy_mask);
buff_tmp[5] = SYS_TO_LE_U32(cmd->target_addr);
buff_tmp[6] = SYS_TO_LE_U32(cmd->ram_addr);
switch (cmd->data_type)
{
case 0:
buff_tmp[7] = STM32_FL_DATATYPE_0;
break;
case 1:
buff_tmp[7] = STM32_FL_DATATYPE_BYTE;
break;
case 2:
buff_tmp[7] = STM32_FL_DATATYPE_HWORD;
break;
case 4:
buff_tmp[7] = STM32_FL_DATATYPE_WORD;
break;
case 8:
buff_tmp[7] = STM32_FL_DATATYPE_DWORD;
break;
default:
return VSFERR_FAIL;
}
buff_tmp[7] |= SYS_TO_LE_U16(cmd->data_round) << 16;
buff_tmp[8] = SYS_TO_LE_U16(cmd->data_unit_round);
buff_tmp[9] = SYS_TO_LE_U32(1);
// write fl command with sync to target SRAM
// sync is 4-byte AFTER command in sram
if (adi_memap_write_buf32(fl->base + STM32_FL_COMMAND_OFFSET,
(uint8_t*)buff_tmp, sizeof(buff_tmp)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load flashloader cmd to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
fl->cnt++;
return VSFERR_NONE;
}
vsf_err_t stm32swj_fl_init(struct stm32_fl_t *fl)
{
uint32_t reg;
uint8_t verify_buff[sizeof(fl_code)];
// download flash_loader
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt stm32");
return ERRCODE_FAILURE_OPERATION;
}
// write code to target SRAM
if (adi_memap_write_buf32(fl->base, fl_code, sizeof(fl_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load flash_loader to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify fl_code
memset(verify_buff, 0, sizeof(fl_code));
if (adi_memap_read_buf32(fl->base, verify_buff, sizeof(fl_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, fl_code, sizeof(fl_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
reg = fl->base + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
fl->cnt = 0;
return VSFERR_NONE;
}
static vsf_err_t kinetisswj_iap_run(struct kinetis_fl_t *fl,
struct kinetisswj_iap_cmd_t *cmd)
{
uint32_t buff_tmp[5];
buff_tmp[0] = SYS_TO_LE_U32(cmd->reg_base); // reg base
buff_tmp[1] = SYS_TO_LE_U32(cmd->fccob[0]); // iap parameters
buff_tmp[2] = SYS_TO_LE_U32(cmd->fccob[1]);
buff_tmp[3] = SYS_TO_LE_U32(cmd->fccob[2]);
// sync is word AFTER command in sram
buff_tmp[4] = SYS_TO_LE_U32(1); // sync
// write iap command with sync to target SRAM
if (adi_memap_write_buf32(KINETIS_IAP_COMMAND_ADDR,
(uint8_t*)buff_tmp, sizeof(buff_tmp)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap cmd to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
fl->iap_cnt++;
return VSFERR_NONE;
}
static vsf_err_t nuc400swj_init_iap(void)
{
uint32_t reg;
uint8_t verify_buff[sizeof(iap_code)];
uint32_t fuse_data[4];
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt nuc400");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_unlock())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "unlock NUC chip");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_fmc_enable())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "enable FMC");
return ERRCODE_FAILURE_OPERATION;
}
chip_protected = false;
if (nuc400swj_isp_run(NUC400_REG_ISPCMD_READ,
NUC400_REG_CFG_BA, (uint32_t *)fuse_data, 4, true))
{
return ERRCODE_FAILURE_OPERATION;
}
if ((fuse_data[0] != 0xFFFFFFFF) || (fuse_data[1] != 0xFFFFFFFF) ||
(fuse_data[2] != 0xFFFFFFFF))
{
uint32_t crc32 = 0;
struct crc_t crc8 = {CRC_BITLEN_8, 0xFF, 0x07};
uint8_t *fuse_byte = (uint8_t *)fuse_data;
uint8_t i;
for (i = 0; i < 4; i++)
{
crc8.result = 0xFF;
crc_calc(&crc8, &fuse_byte[i + 0], 1);
crc_calc(&crc8, &fuse_byte[i + 4], 1);
crc_calc(&crc8, &fuse_byte[i + 8], 1);
crc32 |= crc8.result << (i * 8);
}
if (crc32 == fuse_data[3])
{
// checksum ok, option bytes valid
// check if read protected
if (!(fuse_data[0] & 0x00000002))
{
// read protected
chip_protected = true;
LOG_INFO("chip protected");
return VSFERR_NONE;
}
}
}
// write iap_code
if (adi_memap_write_buf32(NUC400_IAP_BASE, (uint8_t*)iap_code,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap_code to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify iap_code
memset(verify_buff, 0, sizeof(iap_code));
if (adi_memap_read_buf32(NUC400_IAP_BASE, verify_buff,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, iap_code, sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
// write pc
reg = NUC400_IAP_BASE + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run iap");
return ERRCODE_FAILURE_OPERATION;
}
return VSFERR_NONE;
}