static int ag7240_recv(struct eth_device *dev)
{
int length;
ag7240_desc_t *f;
ag7240_mac_t *mac;
mac = (ag7240_mac_t *)dev->priv;
for (;;) {
f = mac->fifo_rx[mac->next_rx];
if (ag7240_rx_owned_by_dma(f))
break;
length = f->pkt_size;
NetReceive(NetRxPackets[mac->next_rx] , length - 4);
flush_cache((u32) NetRxPackets[mac->next_rx] , PKTSIZE_ALIGN);
ag7240_rx_give_to_dma(f);
if (++mac->next_rx >= NO_OF_RX_FIFOS)
mac->next_rx = 0;
}
if (!(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))) {
ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(f));
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1);
}
return (0);
}
/*
* For every command we re-setup the ring and start with clean h/w rx state
*/
static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd) {
int i;
ag7240_desc_t *fr;
ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv;
if (!ag7240_check_link(mac)){
return 0;
}
mac->next_rx = 0;
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
fr = mac->fifo_rx[i];
fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);
flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
ag7240_rx_give_to_dma(fr);
}
ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE);
/* rx start */
if (!is_ar933x()){
// TODO: do we need this?
udelay(1000 * 1000);
}
return 1;
}
/*
* For every command we re-setup the ring and start with clean h/w rx state
*/
static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd)
{
int i;
ag7240_desc_t *fr;
ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv;
if (!ag7240_check_link(mac))
return 0;
mac->next_rx = 0;
/**
* @ when executing TFTP transfers at -10C
* @ time taken for auto negotiation and link to settled down
* @ is quite high. provide 3 Sec delay for s17 link to settle
* @ down. Works fine at room temparature, 0C -3C
@ Suggested by systems team.
*/
#ifdef CONFIG_ATHRS17_PHY
udelay(1000 * 3000);
#endif
ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN |
AG7240_MAC_CFG1_TX_EN));
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
fr = mac->fifo_rx[i];
fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);
flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
ag7240_rx_give_to_dma(fr);
}
ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE); /* rx start */
udelay(1000 * 1000);
return 1;
}