static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
{
struct pci_dev *device = NULL;
u32 command;
int rate;
dev_info(&agp_bridge->dev->dev, "AGP %d.%d bridge\n",
agp_bridge->major_version, agp_bridge->minor_version);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
command = agp_collect_device_status(bridge, mode, command);
command |= AGPSTAT_AGP_ENABLE;
rate = (command & 0x7) << 2;
for_each_pci_dev(device) {
u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
if (!agp)
continue;
dev_info(&agp_bridge->dev->dev, "putting AGP V3 device at %s into %dx mode\n",
pci_name(device), rate);
pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
/*
* Weird: on some sis chipsets any rate change in the target
* command register triggers a 5ms screwup during which the master
* cannot be configured
*/
if (device->device == bridge->dev->device) {
dev_info(&agp_bridge->dev->dev, "SiS delay workaround: giving bridge time to recover\n");
msleep(10);
}
}
}
static void uninorth_agp_enable(u32 mode)
{
u32 command, scratch;
int timeout;
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
uninorth_tlbflush(NULL);
timeout = 0;
do {
pci_write_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
command);
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
&scratch);
} while ((scratch & 0x100) == 0 && ++timeout < 1000);
if ((scratch & 0x100) == 0)
printk(KERN_ERR PFX "failed to write UniNorth AGP command reg\n");
agp_device_command(command, 0);
uninorth_tlbflush(NULL);
}
static void alpha_core_agp_enable(u32 mode)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw);
agp->mode.bits.enable = 1;
agp->ops->configure(agp);
agp_device_command(agp->mode.lw, 0);
}
static void
hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
{
struct _hp_private *hp = &hp_private;
u32 command;
command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
command = agp_collect_device_status(bridge, mode, command);
command |= 0x00000100;
writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
agp_device_command(command, (mode & AGP8X_MODE) != 0);
}
static void
hp_zx1_enable (u32 mode)
{
struct _hp_private *hp = &hp_private;
u32 command;
command = INREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_STATUS);
command = agp_collect_device_status(mode, command);
command |= 0x00000100;
OUTREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_COMMAND, command);
agp_device_command(command, (mode & AGP8X_MODE) != 0);
}
void agp_generic_enable(u32_t requested_mode)
{
u32_t bridge_agpstat, temp;
get_agp_version(bridge);
dbgprintf("Found an AGP %d.%d compliant device.\n",
bridge->major_version, bridge->minor_version);
bridge_agpstat = pciReadLong(bridge->PciTag,
bridge->capndx + PCI_AGP_STATUS);
bridge_agpstat = agp_collect_device_status(bridge, requested_mode, bridge_agpstat);
if (bridge_agpstat == 0)
/* Something bad happened. FIXME: Return error code? */
return;
bridge_agpstat |= AGPSTAT_AGP_ENABLE;
/* Do AGP version specific frobbing. */
if (bridge->major_version >= 3)
{
if (bridge->mode & AGPSTAT_MODE_3_0)
{
/* If we have 3.5, we can do the isoch stuff. */
if (bridge->minor_version >= 5)
agp_3_5_enable(bridge);
agp_device_command(bridge_agpstat, TRUE);
return;
}
else
{
/* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
bridge_agpstat &= ~(7<<10) ;
temp = pciReadLong(bridge->PciTag, bridge->capndx+AGPCTRL);
temp |= (1<<9);
pciWriteLong(bridge->PciTag, bridge->capndx+AGPCTRL, temp);
dbgprintf("Device is in legacy mode,"
" falling back to 2.x\n");
}
}
/* AGP v<3 */
agp_device_command(bridge_agpstat, FALSE);
}
static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
u32 command;
pci_read_config_dword(serverworks_private.svrwrks_dev,
bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(bridge, mode, command);
command &= ~0x10; /* disable FW */
command &= ~0x08;
command |= 0x100;
pci_write_config_dword(serverworks_private.svrwrks_dev,
bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, false);
}
static void sis_648_enable(u32 mode)
{
struct pci_dev *device = NULL;
u32 command;
int rate;
printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n",
agp_bridge->major_version,
agp_bridge->minor_version,
agp_bridge->dev->slot_name);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
command = agp_collect_device_status(mode, command);
command |= AGPSTAT_AGP_ENABLE;
rate = (command & 0x7) << 2;
while ((device = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, device)) != NULL) {
u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
if (!agp)
continue;
printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n",
pci_name(device), rate);
pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
/*
* Weird: on 648(fx) and 746(fx) chipsets any rate change in the target
* command register triggers a 5ms screwup during which the master
* cannot be configured
*/
if (device->device == PCI_DEVICE_ID_SI_648 ||
device->device == PCI_DEVICE_ID_SI_746) {
printk(KERN_INFO PFX "SiS chipset with AGP problems detected. Giving bridge time to recover.\n");
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout (1+(HZ*10)/1000);
}
}
}
