void si_pmu_init(struct si_pub *sih)
{
struct bcma_device *core;
/* */
core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
if (ai_get_pmurev(sih) == 1)
bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
~PCTL_NOILP_ON_WAIT);
else if (ai_get_pmurev(sih) >= 2)
bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
}
u32 si_pmu_measure_alpclk(struct si_pub *sih)
{
struct si_info *sii = container_of(sih, struct si_info, pub);
struct bcma_device *core;
u32 alp_khz;
if (ai_get_pmurev(sih) < 10)
return 0;
/* Remember original core before switch to chipc */
core = sii->icbus->drv_cc.core;
if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
u32 ilp_ctr, alp_hz;
/*
* Enable the reg to measure the freq,
* in case it was disabled before
*/
bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
/* Delay for well over 4 ILP clocks */
udelay(1000);
/* Read the latched number of ALP ticks per 4 ILP ticks */
ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
PMU_XTALFREQ_REG_ILPCTR_MASK;
/*
* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
* bit to save power
*/
bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
/* Calculate ALP frequency */
alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
/*
* Round to nearest 100KHz, and at
* the same time convert to KHz
*/
alp_khz = (alp_hz + 50000) / 100000 * 100;
} else
alp_khz = 0;
return alp_khz;
}
u32 si_pmu_measure_alpclk(struct si_pub *sih)
{
struct bcma_device *core;
u32 alp_khz;
if (ai_get_pmurev(sih) < 10)
return 0;
/* */
core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
u32 ilp_ctr, alp_hz;
/*
*/
bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
/* */
udelay(1000);
/* */
ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
PMU_XTALFREQ_REG_ILPCTR_MASK;
/*
*/
bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
/* */
alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
/*
*/
alp_khz = (alp_hz + 50000) / 100000 * 100;
} else
alp_khz = 0;
return alp_khz;
}
