// Trim DAC write
void dac_write( uint16_t val ) {
// alt_printf( "DAC Writing: %x\n", val ) ;
uint8_t data[3] ;
data[0] = 0x28, data[1] = 0, data[2] = 0 ;
alt_avalon_spi_command( SPI_1_BASE, 0, 3, data, 0, 0, 0 ) ;
data[0] = 0x08, data[1] = (val>>8)&0xff, data[2] = val&0xff ;
alt_avalon_spi_command( SPI_1_BASE, 0, 3, data, 0, 0, 0) ;
return ;
}
static void demo_showinputs(void)
{
int channel;
alt_u8 temp[4] = {0};
char text[64];
lcd_rect(0, 0, LCD_WIDTH, LCD_HEIGHT, COLOR_WHITE);
do
{
strcpy(text,
"GPIO0 = 0\r\n" // 8
"GPIO1 = 0\r\n" // 19
"GPI2 = 0\r\n"); // 30
temp[0] = gpio_lcd_readall();
text[ 8] += (temp[0] >> 0) & 1;
text[19] += (temp[0] >> 1) & 1;
text[30] += (IORD_ALTERA_AVALON_PIO_DATA(PIO_GPIO2IN_BASE) >> 2) & 1;
lcd_puts(text, 10, 10, COLOR_BLACK, COLOR_WHITE);
strcpy(text, "AIN0 = 0x--- (with *P driver)");
temp[0] = temp[1] = 0;
for(channel = 0; channel < 8; ++channel)
{
if(channel < 4)
text[13] = 0;
else if(channel < 6)
{
// Drive YP and YN
gpio_lcd_reg_modify(REG_OLAT, (1<<LCD_GPIO_YN), (1<<LCD_GPIO_YP));
gpio_lcd_reg_modify(REG_IODIR, (1<<LCD_GPIO_YN)|(1<<LCD_GPIO_YP), 0);
text[13] = ' ';
text[20] = 'Y';
}
else
{
// Drive XP and XN
gpio_lcd_reg_modify(REG_OLAT, (1<<LCD_GPIO_XN), (1<<LCD_GPIO_XP));
gpio_lcd_reg_modify(REG_IODIR, (1<<LCD_GPIO_XN)|(1<<LCD_GPIO_XP), 0);
text[13] = ' ';
text[20] = 'X';
}
temp[0] = (channel << 3);
alt_avalon_spi_command(SPIM_ADC_BASE, 0, 2, temp, 2, temp + 2, 0);
if(channel >= 4)
{
// Turn off X/Y driver
gpio_lcd_reg_modify(REG_IODIR, 0, (1<<LCD_GPIO_XN)|(1<<LCD_GPIO_XP)|
(1<<LCD_GPIO_YN)|(1<<LCD_GPIO_YP));
}
text[3] = '0' + channel;
text[10] = tohex[(temp[2] >> 0) & 0xf];
text[11] = tohex[(temp[3] >> 4) & 0xf];
text[12] = tohex[(temp[3] >> 0) & 0xf];
lcd_puts(text, 10, 60 + 10 * channel, COLOR_BLACK, COLOR_WHITE);
}
}
while(DEMO_MODE() == DEMO_SHOWINPUTS);
}
// SPI Read
void lms_spi_read( uint8_t address, uint8_t *val )
{
uint8_t rv ;
if( address > 0x7f )
{
// alt_printf( "Invalid read address: %x\n", address ) ;
} else {
alt_avalon_spi_command( SPI_0_BASE, 0, 1, &address, 0, 0, ALT_AVALON_SPI_COMMAND_MERGE ) ;
rv = alt_avalon_spi_command( SPI_0_BASE, 0, 0, 0, 1, val, 0 ) ;
if( rv != 1 )
{
// alt_putstr( "SPI data read did not work :(\n") ;
}
}
if( LMS_VERBOSE )
{
// alt_printf( "r-addr: %x data: %x\n", address, *val ) ;
}
return ;
}
void spiAnalog(alt_u8 *read_data)
{
alt_u32 slave, write_length, read_length, flags;
const alt_u8 *write_data = 0;
flags = 0;
read_length = 2; //2 Bytes lesen
slave = 0;
write_length = 1; //1 Byte schreiben
alt_avalon_spi_command(SPI_BASE, slave, write_length, write_data, read_length, read_data, flags);
}
// SPI Write
void lms_spi_write( uint8_t address, uint8_t val )
{
if( LMS_VERBOSE )
{
// alt_printf( "w-addr: %x data: %x\n", address, val ) ;
}
/*if( address > 0x7f )
{
alt_printf( "Invalid write address: %x\n", address ) ;
} else*/ {
uint8_t data[2] = { address |= LMS_WRITE, val } ;
alt_avalon_spi_command( SPI_0_BASE, 0, 2, data, 0, 0, 0 ) ;
}
return ;
}
static int TestEpcs(void) {
alt_u8 writebuf[8];
alt_u8 readbuf[8];
writebuf[0] = 0xab; // OPCODE
writebuf[1] = 0xff; // dummy byte
writebuf[2] = 0xff; // dummy byte
writebuf[3] = 0xff; // dummy byte
alt_avalon_spi_command(
EPCS_SPI_BASE, 0,
4, writebuf,
1, readbuf,
0);
printf("EPCS Silicon ID = 0x%02X\n", readbuf[0]);
return 0;
}
// Transverter write
void adf4351_write( uint32_t val ) {
union {
uint32_t val;
uint8_t byte[4];
} sval;
uint8_t t;
sval.val = val;
t = sval.byte[0];
sval.byte[0] = sval.byte[3];
sval.byte[3] = t;
t = sval.byte[1];
sval.byte[1] = sval.byte[2];
sval.byte[2] = t;
alt_avalon_spi_command( SPI_1_BASE, 1, 4, &sval.val, 0, 0, 0 ) ;
return ;
}
void camera_init(alt_u32 SPI_BASE) {
alt_u8 sentwrite[2];
alt_u8 received = 0;
sentwrite[1] = 44;
sentwrite[0] = 103 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 4;
sentwrite[0] = 84 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 1;
sentwrite[0] = 85 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 64;
sentwrite[0] = 88 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 64;
sentwrite[0] = 91 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 101;
sentwrite[0] = 94 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 109;
sentwrite[0] = 98 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 109;
sentwrite[0] = 99 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 106;
sentwrite[0] = 95 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 1;
sentwrite[0] = 117 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 1;
sentwrite[0] = 115 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 7;
sentwrite[0] = 82 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//adjusting registers for optimal performance
sentwrite[1] = 44; //req:44, valid:40-55
sentwrite[0] = 103 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 109; //req:109, valid:102-115
sentwrite[0] = 98 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
sentwrite[1] = 109; //req:109, valid:102-115
sentwrite[0] = 99 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//channel mode 0=16 channels; 1=8 channels; 2=4 channels; 3=2 channels
sentwrite[1] = 2;
sentwrite[0] = 72 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
// request amount of frames
sentwrite[1] = 10;
sentwrite[0] = 70 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// training pattern 1
sentwrite[1] = 0x00; //0b01010101
sentwrite[0] = 78 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
// training pattern 2
sentwrite[1] = 0x02;
sentwrite[0] = 79 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// //number of lines 1 255
// sentwrite[1] = 0x30; //0x40
// sentwrite[0] = 1 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// //number of lines 2 1
// sentwrite[1] = 0x04; //0x04
// sentwrite[0] = 2 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
////
// //start row window 1
// sentwrite[1] = 0x00; //0x00
// sentwrite[0] = 3 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// //start row window 2
// sentwrite[1] = 0x00; //0x00
// sentwrite[0] = 4 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// // row skip 1
// sentwrite[1] = 0x00; //0x00
// sentwrite[0] = 35 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// // row skip 2
// sentwrite[1] = 0x00; //0x00
// sentwrite[0] = 37 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//bit mode
sentwrite[1] = 0x01;
sentwrite[0] = 111 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
// image flipping x/y
sentwrite[1] = 0x01; //0x01: image flipping x
sentwrite[0] = 40 | 0x80;
alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
// // exposure time 1
// sentwrite[1] = 0x00; //0x40
// sentwrite[0] = 42 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// // exposure time 2
// sentwrite[1] = 0x04; //0x04
// sentwrite[0] = 43 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
//
// // exposure time 3
// sentwrite[1] = 0x00; //0x00
// sentwrite[0] = 44 | 0x80;
// alt_avalon_spi_command(SPI_BASE, 0, 2, sentwrite, 0, &received, 0);
}