void spl_board_init(void) { /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ save_omap_boot_params(); /* Prepare console output */ preloader_console_init(); #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif #ifdef CONFIG_AM33XX am33xx_spl_board_init(); #endif }
void spl_board_init(void) { #ifdef CONFIG_SPL_NAND_SUPPORT gpmc_init(); #endif #ifdef CONFIG_AM33XX am33xx_spl_board_init(); #endif }
void spl_board_init(void) { #ifdef CONFIG_SPL_NAND_SUPPORT gpmc_init(); #endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif #ifdef CONFIG_AM33XX am33xx_spl_board_init(); #endif }
/* * early system init of muxing and clocks. */ void s_init(void) { __maybe_unused struct am335x_baseboard_id header; #ifdef CONFIG_NOR_BOOT asm("stmfd sp!, {r2 - r4}"); asm("movw r4, #0x8A4"); asm("movw r3, #0x44E1"); asm("orr r4, r4, r3, lsl #16"); asm("mov r2, #9"); asm("mov r3, #8"); asm("gpmc_mux: str r2, [r4], #4"); asm("subs r3, r3, #1"); asm("bne gpmc_mux"); asm("ldmfd sp!, {r2 - r4}"); #endif /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ writel(0xAAAA, &wdtimer->wdtwspr); while (readl(&wdtimer->wdtwwps) != 0x0) ; writel(0x5555, &wdtimer->wdtwspr); while (readl(&wdtimer->wdtwwps) != 0x0) ; #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) /* Setup the PLLs and the clocks for the peripherals */ pll_init(); /* Enable RTC32K clock */ rtc32k_enable(); /* UART softreset */ u32 regVal; enable_uart0_pin_mux(); regVal = readl(&uart_base->uartsyscfg); regVal |= UART_RESET; writel(regVal, &uart_base->uartsyscfg); while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) ; /* Disable smart idle */ regVal = readl(&uart_base->uartsyscfg); regVal |= UART_SMART_IDLE_EN; writel(regVal, &uart_base->uartsyscfg); #if defined(CONFIG_NOR_BOOT) /* NOR booting - enable serial console */ gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07); gd->baudrate = CONFIG_BAUDRATE; serial_init(); gd->have_console = 1; #else gd = &gdata; preloader_console_init(); #endif /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #ifndef CONFIG_NOR_BOOT if (read_eeprom() < 0) puts("Could not get board ID.\n"); #endif /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { puts("Could not probe the EEPROM; something fundamentally " "wrong on the I2C bus.\n"); } /* read the eeprom using i2c */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, sizeof(header))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); } if (header.magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)&header, sizeof(header))) { puts("Could not read the EEPROM; something " "fundamentally wrong on the I2C bus.\n"); hang(); } if (header.magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM\n", header.magic); hang(); } } enable_board_pin_mux(&header); if (!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. */ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); gpio_direction_output(GPIO_DDR_VTT_EN, 1); } #ifdef CONFIG_NOR_BOOT am33xx_spl_board_init(); #endif /* The following boards are known to use DDR3. */ if ((!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) || (!strncmp("A33515BB", header.name, 8) && strncmp("1.5", header.version, 3) <= 0)) config_ddr(EMIF_REG_SDRAM_TYPE_DDR3); else config_ddr(EMIF_REG_SDRAM_TYPE_DDR2); #endif }