/*
* Processing of HW TX descriptor.
*/
HAL_STATUS
ar5416ProcTxDesc(struct ath_hal *ah, void *desc)
{
struct ar5416_desc *ads = AR5416DESC(desc);
struct ath_desc *ds = (struct ath_desc *)desc;
struct ath_tx_status *ntxstat;
#ifdef AH_NEED_DESC_SWAP
if ((ads->ds_txstatus9 & __bswap32(AR_TxDone)) == 0)
return HAL_EINPROGRESS;
ar5416SwapTxDesc(ds);
#else
if ((ads->ds_txstatus9 & AR_TxDone) == 0)
return HAL_EINPROGRESS;
#endif
/*
* Use a local copy of ds/ads in the cacheable memory to
* improve the d-cache efficiency
*/
ntxstat = &(ds->ds_txstat);
/* Update software copies of the HW status */
ntxstat->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
ntxstat->ts_tstamp = ads->AR_SendTimestamp;
ntxstat->ts_status = 0;
ntxstat->ts_flags = 0;
if (ads->ds_txstatus1 & AR_ExcessiveRetries)
ntxstat->ts_status |= HAL_TXERR_XRETRY;
if (ads->ds_txstatus1 & AR_Filtered)
ntxstat->ts_status |= HAL_TXERR_FILT;
if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
ntxstat->ts_status |= HAL_TXERR_FIFO;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus9 & AR_TxOpExceeded)
ntxstat->ts_status |= HAL_TXERR_XTXOP;
if (ads->ds_txstatus1 & AR_TxTimerExpired)
ntxstat->ts_status |= HAL_TXERR_TIMER_EXPIRED;
if (ads->ds_txstatus1 & AR_DescCfgErr)
ntxstat->ts_flags |= HAL_TX_DESC_CFG_ERR;
if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
ntxstat->ts_flags |= HAL_TX_DATA_UNDERRUN;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
ntxstat->ts_flags |= HAL_TX_DELIM_UNDERRUN;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus0 & AR_TxBaStatus) {
ntxstat->ts_flags |= HAL_TX_BA;
ntxstat->ba_low = ads->AR_BaBitmapLow;
ntxstat->ba_high = ads->AR_BaBitmapHigh;
}
ntxstat->tid = (ads->ds_txstatus9 & 0xf0000000) >>28;
/*
* Extract the transmit rate.
*/
ntxstat->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
switch (ntxstat->ts_rateindex) {
case 0:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
break;
case 1:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
break;
case 2:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
break;
case 3:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
break;
}
ntxstat->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
ntxstat->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
ntxstat->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
ntxstat->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
ntxstat->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
ntxstat->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
ntxstat->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
ntxstat->evm0 = ads->AR_TxEVM0;
ntxstat->evm1 = ads->AR_TxEVM1;
ntxstat->evm2 = ads->AR_TxEVM2;
ntxstat->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
ntxstat->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
ntxstat->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
ntxstat->ts_antenna = 0;
return HAL_OK;
}
HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
{
struct ar5416_desc *ads = AR5416DESC(gds);
struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
if ((ads->ds_txstatus9 & AR_TxDone) == 0)
return HAL_EINPROGRESS;
ads->ds_txstatus9 &= ~AR_TxDone;
/* Update software copies of the HW status */
ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
ds->ds_txstat.ts_status = 0;
ds->ds_txstat.ts_flags = 0;
if (ads->ds_txstatus1 & AR_ExcessiveRetries)
ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
if (ads->ds_txstatus1 & AR_Filtered)
ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
if (ads->ds_txstatus1 & AR_FIFOUnderrun)
ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
if (ads->ds_txstatus9 & AR_TxOpExceeded)
ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
if (ads->ds_txstatus1 & AR_TxTimerExpired)
ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
if (ads->ds_txstatus1 & AR_DescCfgErr)
ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus0 & AR_TxBaStatus) {
ds->ds_txstat.ts_flags |= HAL_TX_BA;
ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
}
/*
* Extract the transmit rate used and mark the rate as
* ``alternate'' if it wasn't the series 0 rate.
*/
ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
ds->ds_txstat.ts_rssi_combined =
MS(ads->ds_txstatus5, AR_TxRSSICombined);
ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
ds->ds_txstat.evm0 = ads->AR_TxEVM0;
ds->ds_txstat.evm1 = ads->AR_TxEVM1;
ds->ds_txstat.evm2 = ads->AR_TxEVM2;
ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
return HAL_OK;
}
