static ssize_t gpio_proc_read(struct file *file, char __user * buffer, size_t size, loff_t * ppos)
{
unsigned int *data = PDE_DATA(file_inode(file));
int val;
unsigned int pin = (unsigned int)data & PIN_MASK;
char buf[2];
if (pin >= 23 && pin <= 31) {
val = nxp_74hc153_get_value(pin - 23);
// printk(KERN_EMERG "value for pin %d = %d\n", pin, val);
if (val)
buf[0] = '1';
else
buf[0] = '0';
buf[1] = 0;
return simple_read_from_buffer(buffer, size, ppos, buf, sizeof(buf));
}
u32 reg = 0;
if ((unsigned int)data & GPIO_IN)
reg = ar7100_reg_rd(AR7100_GPIO_IN);
if ((unsigned int)data & GPIO_OUT)
reg = ar7100_reg_rd(AR7100_GPIO_OUT);
if ((unsigned int)data & GPIO_DIR)
reg = ar7100_reg_rd(AR7100_GPIO_OE);
if (GPIO_CR_M(((unsigned int)data) & PIN_MASK) & reg)
buf[0] = '1';
else
buf[0] = '0';
buf[1] = 0;
return simple_read_from_buffer(buffer, size, ppos, buf, sizeof(buf));
}
void ar7100_gpio_config_int(int gpio,
ar7100_gpio_int_type_t type,
ar7100_gpio_int_pol_t polarity)
{
u32 val;
/*
* allow edge sensitive/rising edge too
*/
if (type == INT_TYPE_LEVEL) {
/* level sensitive */
ar7100_reg_rmw_set(AR7100_GPIO_INT_TYPE, (1 << gpio));
}
else {
/* edge triggered */
val = ar7100_reg_rd(AR7100_GPIO_INT_TYPE);
val &= ~(1 << gpio);
ar7100_reg_wr(AR7100_GPIO_INT_TYPE, val);
}
if (polarity == INT_POL_ACTIVE_HIGH) {
ar7100_reg_rmw_set (AR7100_GPIO_INT_POLARITY, (1 << gpio));
}
else {
val = ar7100_reg_rd(AR7100_GPIO_INT_POLARITY);
val &= ~(1 << gpio);
ar7100_reg_wr(AR7100_GPIO_INT_POLARITY, val);
}
ar7100_reg_rmw_set(AR7100_GPIO_INT_ENABLE, (1 << gpio));
}
int ar7100_get_gpio(int gpio)
{
u32 reg = ar7100_reg_rd(AR7100_GPIO_OE);
reg &= ~(1 << gpio);
ar7100_reg_wr(AR7100_GPIO_OE, reg);
reg = ar7100_reg_rd(AR7100_GPIO_IN);
if (reg & (1 << gpio))
return 1;
else
return 0;
}
void ar7100_set_gpio(int gpio, int val)
{
u32 reg = ar7100_reg_rd(AR7100_GPIO_OE);
reg |= 1 << gpio;
ar7100_reg_wr(AR7100_GPIO_OE, reg);
(void)ar7100_reg_rd(AR7100_GPIO_OE); /* flush write to hardware */
reg = ar7100_reg_rd(AR7100_GPIO_OUT);
if (val)
reg |= 1 << gpio;
else
reg &= ~(1 << gpio);
ar7100_reg_wr(AR7100_GPIO_OUT, reg);
}
int get_wl1_gpio(int gpio)
{
register gpio_words wl1 = (gpio_words) ar7100_reg_rd(GPIO_WL1_ADDR); //ar9280 register [0x4048]
if (wl1 & (1 << gpio)) ;
return 1;
return 0;
}
static int
ar7100fr_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg)
{
int ret = 0;
switch(cmd) {
case AR7100_FACTORY_RESET:
/* Userspace process "factoryreset" is doing IOCTL
* Hope AP is successfully UP
* Turn the power LED on
*/
#ifdef CONFIG_AR9100
#define AP8x_GPIO_POWER_LED (0x01 << 14)
ar7100_reg_wr(AR7100_GPIO_OE, AP8x_GPIO_POWER_LED);
ar7100_reg_wr(AR7100_GPIO_OUT,
((ar7100_reg_rd(AR7100_GPIO_OUT)) | ((AP8x_GPIO_POWER_LED))));
#endif
atomic_inc(&ar7100_fr_status);
sleep_on(&ar7100_fr_wq);
break;
default: ret = -EINVAL;
}
return ret;
}
int __init pbXX_simple_config_init(void)
{
#if AR7100_JUMPSTART_SWITCH_WORKS
#ifdef CONFIG_CUS100
u32 mask = 0;
#endif
int req;
#ifdef CONFIG_CUS100
mask = ar7100_reg_rd(AR7100_MISC_INT_MASK);
ar7100_reg_wr(AR7100_MISC_INT_MASK, mask | (1 << 2)); /* Enable GPIO interrupt mask */
ar7100_gpio_config_int (JUMPSTART_GPIO, INT_TYPE_LEVEL,INT_POL_ACTIVE_HIGH);
ar7100_gpio_intr_enable(JUMPSTART_GPIO);
ar7100_gpio_config_input(JUMPSTART_GPIO);
#else
/* configure GPIO 3 as level triggered interrupt */
ar7100_gpio_config_int (JUMPSTART_GPIO, INT_TYPE_LEVEL,INT_POL_ACTIVE_HIGH);
printk("%s (%s) JUMPSTART_GPIO: %d\n", __FILE__, __func__, JUMPSTART_GPIO);
#endif
req = request_irq (AR7100_GPIO_IRQn(JUMPSTART_GPIO), jumpstart_irq, 0,
"SW JUMPSTART", NULL);
if (req != 0) {
printk (KERN_ERR "unable to request IRQ for SWJUMPSTART GPIO (error %d)\n", req);
}
create_simple_config_led_proc_entry ();
#endif // AR7100_JUMPSTART_SWITCH_WORKS
return 0;
}
unsigned int
generic_spi_raw_input_u8(void)
{
int ii;
unsigned int cs0to2mask = ar7100_reg_rd(GENERIC_SPI_WRITE) & ~(GENERIC_SPI_D0_HIGH|GENERIC_SPI_CLK_HIGH);
/* For each rising edge the data in is sampled and clocked into serial shift register */
for (ii = 7; ii>=0 ; ii--) {
ar7100_reg_wr(GENERIC_SPI_WRITE, cs0to2mask );
ar7100_reg_wr(GENERIC_SPI_WRITE, cs0to2mask | GENERIC_SPI_CLK_HIGH );
}
/* Shift register contains value read */
return ar7100_reg_rd(GENERIC_SPI_RD_SHIFT_REG);
}
int __init ar7100_factory_reset_init(void)
{
#ifdef CONFIG_CUS100
u32 mask = 0;
#endif
int req, ret;
ret = misc_register(&ar7100fr_miscdev);
if (ret < 0) {
printk("*** ar7100 misc_register failed %d *** \n", ret);
return -1;
}
#ifdef CONFIG_CUS100
mask = ar7100_reg_rd(ar7100_MISC_INT_MASK);
ar7100_reg_wr(ar7100_MISC_INT_MASK, mask | (1 << 2)); /* Enable GPIO interrupt mask */
ar7100_gpio_config_int (FACTORY_RESET_GPIO, INT_TYPE_LEVEL,INT_POL_ACTIVE_HIGH);
ar7100_gpio_intr_enable(FACTORY_RESET_GPIO);
ar7100_gpio_config_input(FACTORY_RESET_GPIO);
#else
ar7100_gpio_config_int (FACTORY_RESET_GPIO, INT_TYPE_LEVEL,INT_POL_ACTIVE_HIGH);
#endif
req = request_irq (AR7100_GPIO_IRQn(FACTORY_RESET_GPIO), factory_reset_irq, 0,
"FACTORY RESET", NULL);
if (req != 0) {
printk (KERN_ERR "unable to request IRQ for FACTORY_RESET GPIO (error %d)\n", req);
misc_deregister(&ar7100fr_miscdev);
ar7100_gpio_intr_shutdown(AR7100_GPIO_IRQn(FACTORY_RESET_GPIO));
return -1;
}
init_waitqueue_head(&ar7100_fr_wq);
return 0;
}
void ar7100_gpio_out_val(int gpio, int val)
{
if (val & 0x1) {
ar7100_reg_rmw_set(AR7100_GPIO_OUT, (1 << gpio));
} else {
ar7100_reg_rmw_clear(AR7100_GPIO_OUT, (1 << gpio));
}
(void)ar7100_reg_rd(AR7100_GPIO_OUT); /* flush write to hardware */
}
static ssize_t gpio_proc_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos)
{
u32 reg = 0;
unsigned int *data = PDE_DATA(file_inode(file));
if (!count)
return 0;
/* get buffer size */
procfs_buffer_size = count;
if (procfs_buffer_size > PROCFS_MAX_SIZE) {
procfs_buffer_size = PROCFS_MAX_SIZE;
}
/* write data to the buffer */
if (copy_from_user(procfs_buffer, buffer, procfs_buffer_size)) {
return -EFAULT;
}
procfs_buffer[procfs_buffer_size] = 0;
if ((unsigned int)data & GPIO_IN)
reg = ar7100_reg_rd(AR7100_GPIO_IN);
if ((unsigned int)data & GPIO_OUT)
reg = ar7100_reg_rd(AR7100_GPIO_OUT);
if ((unsigned int)data & GPIO_DIR)
reg = ar7100_reg_rd(AR7100_GPIO_OE);
if (procfs_buffer[0] == '0' || procfs_buffer[0] == 'i')
reg = reg & ~(GPIO_CR_M(((unsigned int)data) & PIN_MASK));
if (procfs_buffer[0] == '1' || procfs_buffer[0] == 'o')
reg = reg | GPIO_CR_M(((unsigned int)data) & PIN_MASK);
if ((unsigned int)data & GPIO_IN) {
ar7100_reg_wr(AR7100_GPIO_IN, reg);
}
if ((unsigned int)data & GPIO_OUT) {
ar7100_reg_wr(AR7100_GPIO_OUT, reg);
}
if ((unsigned int)data & GPIO_DIR) {
ar7100_reg_wr(AR7100_GPIO_OE, reg);
}
return procfs_buffer_size;
}
static void
ar7100_spi_poll()
{
int rd;
do {
ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CS_DIS);
ar7100_spi_bit_banger(AR7100_SPI_CMD_RD_STATUS);
ar7100_spi_delay_8();
rd = (ar7100_reg_rd(AR7100_SPI_RD_STATUS) & 1);
}while(rd);
}
void set_wl1_gpio(int gpio, int val)
{
register gpio_words wl1;
int shift;
wl1 = (gpio_words) ar7100_reg_rd(GPIOOUT_WL0_ADDR);
shift = gpio * 2;
wl1 |= AR_GPIO_OE_OUT_DRV << shift;
ar7100_reg_wr(GPIOOUT_WL1_ADDR, wl1); //ar9283 register [0x4048]
ar7100_reg_rd(GPIOOUT_WL1_ADDR); //ar9283 register [0x4048]
wl1 = (gpio_words) ar7100_reg_rd(GPIO_WL1_ADDR); //ar9280 register [0x4048]
if (val)
wl1 |= 1 << gpio;
else
wl1 &= (~(1 << gpio));
ar7100_reg_wr(GPIO_WL1_ADDR, wl1); //ar9283 register [0x4048]
ar7100_reg_rd(GPIO_WL1_ADDR); //ar9283 register [0x4048]
}
static int
generic_i2c_chigh_dread(void)
{
int d;
ar7100_gpio_float_high_test( GENERIC_I2C_SCL );
ar7100_reg_rmw_clear( AR7100_GPIO_OE, GENERIC_I2C_SDA );
udelay( GENERIC_I2C_PAUSE/2 );
d = (ar7100_reg_rd( AR7100_GPIO_IN ) & GENERIC_I2C_SDA) ? 1 : 0;
udelay ( GENERIC_I2C_PAUSE/2);
return d;
}
void
generic_spi_raw_output_u8(unsigned char val)
{
int ii;
unsigned int cs0to2mask = ar7100_reg_rd(GENERIC_SPI_WRITE) & ~(GENERIC_SPI_D0_HIGH|GENERIC_SPI_CLK_HIGH);
/* Shift out SPI values keeping GPIO bits the same */
for (ii = 7; ii>=0 ; ii--) {
unsigned char jj = (val >> ii) & 1;
ar7100_reg_wr(GENERIC_SPI_WRITE, cs0to2mask | jj );
ar7100_reg_wr(GENERIC_SPI_WRITE, cs0to2mask | jj | GENERIC_SPI_CLK_HIGH );
}
}
static void
read_id()
{
u32 rd = 0x777777;
ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CS_DIS);
ar7100_spi_bit_banger(0x9f);
ar7100_spi_delay_8();
ar7100_spi_delay_8();
ar7100_spi_delay_8();
ar7100_spi_done();
/* rd = ar7100_reg_rd(AR7100_SPI_RD_STATUS); */
rd = ar7100_reg_rd(AR7100_SPI_READ);
printf("id read %#x\n", rd);
}
int
generic_spi_access_enable(int cs)
{
protect();
ar7100_reg_wr(GENERIC_SPI_CLOCK, 0x43);
/* Enable access to SPI bits through memory
* mapped registers.
*/
ar7100_reg_wr_nf(GENERIC_SPI_FS, 1);
ar7100_reg_wr_nf(GENERIC_SPI_WRITE, GENERIC_SPI_CS_DIS);
{
unsigned int cs0to2mask;
cs0to2mask = ar7100_reg_rd(GENERIC_SPI_WRITE) & GENERIC_SPI_CS_DIS;
ar7100_reg_wr (GENERIC_SPI_WRITE, cs0to2mask | GENERIC_SPI_CLK_HIGH );
}
generic_i2c_assert_cs(cs);
return 0;
}
static void ag7100_set_pll(ag7100_mac_t *mac, unsigned int pll)
{
uint32_t shift, reg, val;
shift = ag7100_pll_shift(mac);
reg = ag7100_pll_offset(mac);
val = ar7100_reg_rd(AR7100_USB_PLL_CONFIG);
val &= ~(3 << shift);
val |= (2 << shift);
ar7100_reg_wr(AR7100_USB_PLL_CONFIG, val);
A_UDELAY(100);
ar7100_reg_wr(reg, pll);
val |= (3 << shift);
ar7100_reg_wr(AR7100_USB_PLL_CONFIG, val);
A_UDELAY(100);
val &= ~(3 << shift);
ar7100_reg_wr(AR7100_USB_PLL_CONFIG, val);
A_UDELAY(100);
}
int
ar7100_gpio_in_val(int gpio)
{
return((1 << gpio) & (ar7100_reg_rd(AR7100_GPIO_IN)));
}
void ar7100_gpio_config_input(int gpio)
{
ar7100_reg_rmw_clear(AR7100_GPIO_OE, (1 << gpio));
(void)ar7100_reg_rd(AR7100_GPIO_OE); /* flush write to hardware */
}
static ssize_t gpio_proc_info_read(struct file *file, char __user * buffer, size_t size, loff_t * ppos)
{
char buf[128];
sprintf(buf, "GPIO_IN %#08X \nGPIO_OUT %#08X \nGPIO_DIR %#08X \n", ar7100_reg_rd(AR7100_GPIO_IN), ar7100_reg_rd(AR7100_GPIO_OUT), ar7100_reg_rd(AR7100_GPIO_OE));
return simple_read_from_buffer(buffer, size, ppos, buf, strlen(buf));
}
