/*
* Returns JEDEC ID from SPI flash
*/
static ulong read_id(void){
unsigned int flashid = 0;
ar7240_reg_wr_nf(AR7240_SPI_FS, 1);
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(0x9F);
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_delay_8();
flashid = ar7240_reg_rd(AR7240_SPI_RD_STATUS);
/*
* We have 3 bytes:
* - manufacture ID (1b)
* - product ID (2b)
*/
flashid = flashid >> 8;
ar7240_spi_done();
return((ulong)flashid);
}
int wasp_mem_config(void){
unsigned int reg32;
wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL);
/* Take WMAC out of reset */
reg32 = ar7240_reg_rd(AR7240_RESET);
reg32 = reg32 & ~AR7240_RESET_WMAC;
ar7240_reg_wr_nf(AR7240_RESET, reg32);
/* Switching regulator settings */
ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */
ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */
//wasp_usb_initial_config();
gpio_config();
/* Needed here not to mess with Ethernet clocks */
ath_set_tuning_caps();
// return memory size
return(ar7240_ddr_find_size());
}
static void
ar7240_spi_write_enable()
{
ar7240_reg_wr_nf(AR7240_SPI_FS, 1);
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(AR7240_SPI_CMD_WREN);
ar7240_spi_go();
}
void
ar7240_usb_initial_config(void)
{
#ifndef CONFIG_HORNET_EMU
ar7240_reg_wr_nf(AR7240_USB_PLL_CONFIG, 0x0a04081e);
ar7240_reg_wr_nf(AR7240_USB_PLL_CONFIG, 0x0804081e);
#endif
}
void
ar7240_ddr_tap_set(uint8_t set)
{
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL0, set);
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL1, set);
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL2, set);
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL3, set);
}
void plat_dev_init(void)
{
u32 val;
u32 addr;
u32 BaseAddr = 0x10000000;
u32 CalAddr = WLANCAL;
volatile u16 *calData;
/*
* Copy the device ID from Flash to device config space.
*/
calData = (u16 *)CalAddr;
#ifndef CONFIG_PCI_CONFIG_DATA_IN_OTP
if(calData[0] != 0xa55a && calData[0] != 0x5aa5 )
{
/*
** Board is not calibrated.
*/
#ifndef COMPRESSED_UBOOT
printf("BOARD IS NOT CALIBRATED!!!\n");
#endif
return;
}
#else
return;
#endif
/*
** Need to setup the PCI device to access the internal registers
*/
if ((is_ar7241() || is_ar7242()))
ar7240_pci_write_config(&hose, NULL, 0x10, 0x1000ffff);
else
ar7240_pci_write_config(&hose, NULL, 0x10, 0xffff);
ar7240_pci_write_config(&hose, NULL, 0x04, 0x6);
/*
** Set pointer to first reg address
*/
calData += AR7240_ART_PCICFG_OFFSET;
while(*calData != 0xffff)
{
u16 cd;
cd = *calData++;
addr = BaseAddr + cd;
val = *calData++;
val |= (*calData++) << 16;
ar7240_reg_wr_nf(addr,val);
udelay(100);
}
return;
}
unsigned long flash_init(void)
{
#ifndef CONFIG_WASP
#ifdef ATH_SST_FLASH
ar7240_reg_wr_nf(AR7240_SPI_CLOCK, 0x3);
ar7240_spi_flash_unblock();
ar7240_reg_wr(AR7240_SPI_FS, 0);
#else
ar7240_reg_wr_nf(AR7240_SPI_CLOCK, 0x43);
#endif
#endif
read_id();
/*
* hook into board specific code to fill flash_info
*/
return (flash_get_geom(&flash_info[0]));
}
static void ar7240_spi_poll(){
int rd;
do {
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(AR7240_SPI_CMD_RD_STATUS);
ar7240_spi_delay_8();
rd = (ar7240_reg_rd(AR7240_SPI_RD_STATUS) & 1);
} while(rd);
}
void
wasp_usb_initial_config(void)
{
#define unset(a) (~(a))
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_SWITCH_CLOCK_SPARE,
ar7240_reg_rd(AR934X_SWITCH_CLOCK_SPARE) |
SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(2));
} else {
ar7240_reg_wr_nf(AR934X_SWITCH_CLOCK_SPARE,
ar7240_reg_rd(AR934X_SWITCH_CLOCK_SPARE) |
SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(5));
}
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) |
RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(1));
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) &
unset(RST_RESET_USB_PHY_RESET_SET(1)));
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) &
unset(RST_RESET_USB_PHY_ARESET_SET(1)));
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) &
unset(RST_RESET_USB_HOST_RESET_SET(1)));
udelay(1000);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
/* Only for WASP 1.0 */
ar7240_reg_wr(0xb8116c84 ,
ar7240_reg_rd(0xb8116c84) & unset(1<<20));
}
}
int
wasp_mem_config(void)
{
unsigned int type, reg32;
type = wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL);
/* Take WMAC out of reset */
reg32 = ar7240_reg_rd(AR7240_RESET);
reg32 = reg32 & ~AR7240_RESET_WMAC;
ar7240_reg_wr_nf(AR7240_RESET, reg32);
/* Switching regulator settings */
ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */
#if !defined(CONFIG_ATH_NAND_BR)
if (ar7240_reg_rd(AR7240_REV_ID) & 0xf) {
if (type == 2) {
// ddr1
ar7240_reg_wr_nf(0x18116c44, 0x10000000); /* AR_PHY_PMU2 */
} else {
// ddr2 & sdram
ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */
}
} else {
ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */
}
#endif
wasp_usb_initial_config();
wasp_gpio_config();
reg32 = ar7240_ddr_find_size();
return reg32;
}
static void
read_id(void)
{
u32 rd = 0x777777;
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(0x9f);
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_done();
/* rd = ar7240_reg_rd(AR7240_SPI_RD_STATUS); */
rd = ar7240_reg_rd(AR7240_SPI_READ);
printf("id read %#x\n", rd);
}
static void
ath_spi_read_id(void)
{
u32 rd = 0x777777;
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(AR7240_SPI_CMD_RDID);
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_go();
rd = ar7240_reg_rd(AR7240_SPI_RD_STATUS);
printf("Flash Manuf Id 0x%x, DeviceId0 0x%x, DeviceId1 0x%x\n",
(rd >> 16) & 0xff, (rd >> 8) & 0xff, (rd >> 0) & 0xff);
}
void
ar7240_usb_initial_config(void)
{
ar7240_reg_wr_nf(AR7240_USB_PLL_CONFIG, 0x0a04081e);
ar7240_reg_wr_nf(AR7240_USB_PLL_CONFIG, 0x0804081e);
}
void
ar7240_ddr_initial_config(uint32_t refresh)
{
int ddr2 = 0,ddr_config;
int ddr_config2,ext_mod,ddr2_ext_mod;
int mod_val,mod_val_init;
#ifndef COMPRESSED_UBOOT
printf("\nsri\n");
#endif
#if 0
ar7240_reg_wr(AR7240_RESET, AR7240_RESET_DDR);
udelay(10);
#endif
ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0);
#ifdef ENABLE_DYNAMIC_CONF
if(*(volatile int *)CFG_DDR_MAGIC_F == CFG_DDR_MAGIC){
ddr_config = CFG_DDR_CONFIG_VAL_F;
ddr_config2 = CFG_DDR_CONFIG2_VAL_F;
ext_mod = CFG_DDR_EXT_MODE_VAL_F;
ddr2_ext_mod = ext_mod;
}
else
#endif
{
#ifdef CONFIG_SUPPORT_AR7241
if (is_ar7241() || is_ar7242()) {
if (ddr2) {
#ifndef COMPRESSED_UBOOT
printf("%s(%d): virian ddr2 init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_7241_DDR2_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR2_CONFIG2_VAL;
#if defined(ENABLE_DYNAMIC_CONF) && (defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3))
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_7241_DDR2_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR2_MODE_VAL_INIT;
mod_val = CFG_7241_DDR2_MODE_VAL;
} else {
#ifndef COMPRESSED_UBOOT
printf("%s(%d): virian ddr1 init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_7241_DDR1_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR1_CONFIG2_VAL;
#if defined(ENABLE_DYNAMIC_CONF) && (defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3))
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_7241_DDR1_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR1_MODE_VAL_INIT;
mod_val = CFG_7241_DDR1_MODE_VAL;
}
}
else
#endif
{
#ifndef COMPRESSED_UBOOT
printf("%s(%d): python ddr init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_DDR_CONFIG_VAL;
ddr_config2 = CFG_DDR_CONFIG2_VAL;
#if (defined(CONFIG_WNR1000V2) || defined(CONFIG_WNR1100) || defined(CONFIG_WNR612)) && defined(ENABLE_DYNAMIC_CONF)
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_DDR_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_DDR_MODE_VAL_INIT;
mod_val = CFG_DDR_MODE_VAL;
}
}
if (ddr2) {
ar7240_reg_wr_nf(0xb800008c, 0xA59);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
udelay(10);
}
#if defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3) || defined(CONFIG_AP121) || defined(CONFIG_WNR1000V4) || defined(CONFIG_HW29763847P16P64)
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
#else
else {
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
uint32_t cmd;
ar7240_reg_rmw_clear(AR7240_RESET,AR7240_RESET_PCIE_PHY_SERIAL);
udelay(100);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0);
udelay(100000);
/*
* Initialize PCIE PLL and get it out of RESET
*/
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x02050800);
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00050800);
udelay(100);
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00040800);
udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4);
udelay(100000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd);
ar7240_local_write_config(0x20, 4, 0x1ff01000);
ar7240_local_write_config(0x24, 4, 0x1ff01000);
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1);
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
#ifdef COMPRESSED_UBOOT
udelay(100);
#else
udelay(1000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
int pci_init_board(void){
uint32_t cmd = 0, reg_val;
reg_val = ar7240_reg_rd(0xb804006c);
ar7240_reg_wr(0xb804006c, reg_val | 2);
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(100000);
/*
if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0){
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0)
);
} else {
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
}
*/
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
/*
if((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0){
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1)
);
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0)
);
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1))
);
pci_udelay(1000);
} else {
*/
ar7240_reg_wr_nf(0xb8116c04, (0x0 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050010, 0x40010800);
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050014, 0xc013fffe);
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050018, 0x00138000);
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050010, 0x00010800);
pci_udelay(100000);
ar7240_reg_wr_nf(0xb8050010, 0x00000800);
pci_udelay(10000);
/*
}
*/
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER |
PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY |
PCI_COMMAND_SERR |
PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
//if((is_ar7241() || is_ar7242() || is_wasp())){
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
//} else {
// ar7240_reg_wr(0x180f0000, 0x1);
//}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
//pci_udelay(100000);
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
// pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
//if(((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0){
// printf("## Error: PCIe WLAN Module not found!\n");
//}
//plat_dev_init();
return(0);
}
void
ar7240_usb_initial_config(void)
{
ar7240_reg_wr_nf(AR7240_USB_PLL_CONFIG, 0x00001030);
}
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
#ifdef CONFIG_AP123
return;
#else
uint32_t cmd = 0, reg_val;
//printf("%s: PCIe PLL 0x%x\n", __func__, mips3_cp0_count_read());
//printf("%s: PCIe PLL 0x%x 0xb8000008 = 0x%08x\n", __func__, mips3_cp0_count_read(), ar7240_reg_rd(0xb8040008));
pci_udelay(100000);
//count ++;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0));
} else {
#ifndef COMPRESSED_UBOOT
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
#endif
}
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0));
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1)));
pci_udelay(1000);
} else {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(2) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(0xb8116c00, (0x5 << 27) | (160 << 18) | 0);
} else {
ar7240_reg_wr_nf(0xb8116c00, (0x2 << 27) | (0x28 << 18) | 0);
}
do {
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (3 << 13) | (0x1e << 7));
ar7240_reg_rmw_clear(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_rmw_set(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(1000);
while (((cmd = ar7240_reg_rd(PCIe_DPLL4_ADDRESS)) & PCIe_DPLL4_MEAS_DONE_SET(1)) == 0) {
printf("0x%x 0x%x 0x%x\n", KSEG1ADDR(PCIe_DPLL4_ADDRESS), cmd);
pci_udelay(10);
}
{ int i; for (i = 0; i < 100; i++) udelay(10); }
#if 0
msdvc = PCIe_DPLL4_MEAN_DVC_GET(cmd);
cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS));
if (msdvc & 0x400) msdvc = ((~msdvc & 0x7FF) + 1); /* 11 bit signed number , but not intentioanlly multiply by (-1), ASK VIPUL*/
msdvc = cmd - (msdvc *msdvc);
msdvc_sq = msdvc * msdvc;
if (cmd >= 0x40000) {
err_count++;
if (sqsum_min_fail == 0)
sqsum_min_fail = cmd;
if (cmd > sqsum_max_fail)
sqsum_max_fail = cmd;
if (cmd < sqsum_min_fail)
sqsum_min_fail = cmd;
sqsum_avg_fail = (sqsum_avg_fail - (sqsum_avg_fail / err_count)) + (cmd / err_count);
if (num_pll_loops == 0)
err_pll1++;
if (num_pll_loops == 1)
err_pll2++;
if (num_pll_loops == 2)
err_pll3++;
if (num_pll_loops == 3)
err_pll4++;
if (num_pll_loops == 4) {
err_pll5++;
break;
}
} else {
if (sqsum_min == 0)
sqsum_min = cmd;
if (cmd < sqsum_min)
sqsum_min = cmd;
if (cmd > sqsum_max)
sqsum_max = cmd;
//sqsum_avg = (sqsum_avg - (sqsum_avg / count)) + (cmd / count);
sqsum_avg += cmd;
/*msdvc calc*/
if (msdvc_min == 0) msdvc_min = msdvc;
if (msdvc < msdvc_min) msdvc_min =msdvc;
if (msdvc > msdvc_max) msdvc_max =msdvc;
msdvc_avg += msdvc;
msdvc_sq_avg += msdvc_sq;
}
num_pll_loops++;
#endif
} while ((cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS))) >= 0x40000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_BYPASS_SET(1));
pci_udelay(10000);
/*
* PCIe Dithering configuration
*/
if (is_ar934x_12_or_later()) {
ar7240_reg_wr_nf(PCIe_DPLL2_ADDRESS,
PCIe_DPLL2_LOCAL_PLL_SET(0) |
PCIe_DPLL2_KI_SET(0x4)|
PCIe_DPLL2_KD_SET(0x40));
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x40010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, 0xc013fffe);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MIN, 0x0013e666);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00000800);
}
//run_command("md 0xb8116c00 4", 0);
}
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
pci_udelay(100000);
#ifdef COMPRESSED_UBOOT
pci_udelay(100);
#else
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#endif // CONFIG_AP123
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
void
ar7240_ddr_initial_config(uint32_t refresh)
{
int ddr2 = 0,ddr_config;
int ddr_config2,ext_mod,ddr2_ext_mod;
int mod_val,mod_val_init;
#if 0
ar7240_reg_wr(AR7240_RESET, AR7240_RESET_DDR);
udelay(10);
#endif
ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0);
#ifdef ENABLE_DYNAMIC_CONF
if(*(volatile int *)CFG_DDR_MAGIC_F == CFG_DDR_MAGIC){
ddr_config = CFG_DDR_CONFIG_VAL_F;
ddr_config2 = CFG_DDR_CONFIG2_VAL_F;
ext_mod = CFG_DDR_EXT_MODE_VAL_F;
ddr2_ext_mod = ext_mod;
}
else
#endif
{
#ifdef CONFIG_SUPPORT_AR7241
if (is_ar7241() || is_ar7242()) {
if (ddr2) {
printf("%s(%d): virian ddr2 init\n", __func__, __LINE__);
ddr_config = CFG_7241_DDR2_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR2_CONFIG2_VAL;
ext_mod = CFG_7241_DDR2_EXT_MODE_VAL;
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR2_MODE_VAL_INIT;
mod_val = CFG_7241_DDR2_MODE_VAL;
} else {
//printf("%s(%d): virian ddr1 init\n", __func__, __LINE__);
ddr_config = CFG_7241_DDR1_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR1_CONFIG2_VAL;
ext_mod = CFG_7241_DDR1_EXT_MODE_VAL;
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR1_MODE_VAL_INIT;
mod_val = CFG_7241_DDR1_MODE_VAL;
}
}
else
#endif
{
printf("%s(%d): python ddr init\n", __func__, __LINE__);
ddr_config = CFG_DDR_CONFIG_VAL;
ddr_config2 = CFG_DDR_CONFIG2_VAL;
ext_mod = CFG_DDR_EXT_MODE_VAL;
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_DDR_MODE_VAL_INIT;
mod_val = CFG_DDR_MODE_VAL;
}
}
if (ddr2) {
ar7240_reg_wr_nf(0xb800008c, 0xA59);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
udelay(10);
}
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init);
udelay(1000);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
udelay(10);
if (ddr2) {
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ddr2_ext_mod);
} else {
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ext_mod);
}
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE,
CFG_DDR_RD_DATA_THIS_CYCLE_VAL);
udelay(100);
}
