/*
* critial i/o space, interrupt, and other chipset related initialization.
*/
void
p_dti_arcstation_init(void)
{
/*
* Initialize interrupt priority
*/
/*
* XXX
* - rewrite spl handling to allow ISA clock > bio|tty|net
* or
* - use MIP3_INTERNAL_TIMER_INTERRUPT for clock
*/
ipl_sr_map = dti_arcstation_ipl_sr_map;
/*
* XXX - should be enabled, if tested.
*
* We use safe default for now, because this platform is untested.
* In other words, the following may not be needed at all.
*/
vm_page_zero_enable = false;
/*
* Initialize I/O address offset
*/
arc_bus_space_init(&arc_bus_io, "rpc44isaio",
RPC44_P_ISA_IO, RPC44_V_ISA_IO, 0, RPC44_S_ISA_IO);
arc_bus_space_init(&arc_bus_mem, "rpc44isamem",
RPC44_P_ISA_MEM, RPC44_V_ISA_MEM, 0, RPC44_S_ISA_MEM);
/*
* Initialize wired TLB for I/O space which is used on early stage
*/
arc_init_wired_map();
/* no need to initialize wired TLB */
/*
* common configuration for DTI platforms
*/
c_isa_init();
#if NPC_ISA > 0 || NOPMS_ISA > 0
/* platform-dependent pccons configuration */
pccons_isa_conf = &pccons_dti_arcstation_conf;
#endif
#if NBTL > 0
/* platform-dependent btl configuration */
btl_conf = &btl_dti_arcstation_conf;
#endif
}
int
vga_jazzio_init_tag(const char *name, bus_space_tag_t *iotp,
bus_space_tag_t *memtp)
{
static int initialized = 0;
static struct arc_bus_space vga_io, vga_mem;
if (strcmp(name, "ALI_S3") != 0)
return ENXIO;
if (!initialized) {
initialized = 1;
arc_bus_space_init(&vga_io, "vga_jazzio_io",
PICA_P_LOCAL_VIDEO_CTRL, PICA_V_LOCAL_VIDEO_CTRL,
0, PICA_S_LOCAL_VIDEO_CTRL);
arc_bus_space_init(&vga_mem, "vga_jazzio_mem",
PICA_P_LOCAL_VIDEO, PICA_V_LOCAL_VIDEO,
0, PICA_S_LOCAL_VIDEO);
arc_wired_enter_page(PICA_V_LOCAL_VIDEO_CTRL,
PICA_P_LOCAL_VIDEO_CTRL,
PICA_S_LOCAL_VIDEO_CTRL / 2);
arc_wired_enter_page(
PICA_V_LOCAL_VIDEO_CTRL + PICA_S_LOCAL_VIDEO_CTRL/2,
PICA_P_LOCAL_VIDEO_CTRL + PICA_S_LOCAL_VIDEO_CTRL/2,
PICA_S_LOCAL_VIDEO_CTRL / 2);
arc_wired_enter_page(PICA_V_LOCAL_VIDEO,
PICA_P_LOCAL_VIDEO,
PICA_S_LOCAL_VIDEO / 2);
arc_wired_enter_page(
PICA_V_LOCAL_VIDEO + PICA_S_LOCAL_VIDEO / 2,
PICA_P_LOCAL_VIDEO + PICA_S_LOCAL_VIDEO / 2,
PICA_S_LOCAL_VIDEO / 2);
#if 0
arc_wired_enter_page(PICA_V_EXTND_VIDEO_CTRL,
PICA_P_EXTND_VIDEO_CTRL,
PICA_S_EXTND_VIDEO_CTRL / 2);
arc_wired_enter_page(
PICA_V_EXTND_VIDEO_CTRL + PICA_S_EXTND_VIDEO_CTRL / 2,
PICA_P_EXTND_VIDEO_CTRL + PICA_S_EXTND_VIDEO_CTRL / 2,
PICA_S_EXTND_VIDEO_CTRL / 2);
#endif
}
*iotp = &vga_io;
*memtp = &vga_mem;
return 0;
}
/*
* Set up the chipset's function pointers.
*/
void
necpb_init(struct necpb_context *ncp)
{
pci_chipset_tag_t pc;
#ifndef PCI_NETBSD_CONFIGURE
pcitag_t tag;
pcireg_t id, class, csr;
u_int dev;
#endif
if (ncp->nc_initialized)
return;
arc_large_bus_space_init(&ncp->nc_memt, "necpcimem",
RD94_P_PCI_MEM, 0, RD94_S_PCI_MEM);
arc_bus_space_init_extent(&ncp->nc_memt, (void *)necpb_mem_ex_storage,
sizeof(necpb_mem_ex_storage));
arc_bus_space_init(&ncp->nc_iot, "necpciio",
RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO);
arc_bus_space_init_extent(&ncp->nc_iot, (void *)necpb_io_ex_storage,
sizeof(necpb_io_ex_storage));
jazz_bus_dma_tag_init(&ncp->nc_dmat);
pc = &ncp->nc_pc;
pc->pc_attach_hook = necpb_attach_hook;
pc->pc_bus_maxdevs = necpb_bus_maxdevs;
pc->pc_make_tag = necpb_make_tag;
pc->pc_decompose_tag = necpb_decompose_tag;
pc->pc_conf_read = necpb_conf_read;
pc->pc_conf_write = necpb_conf_write;
pc->pc_intr_map = necpb_intr_map;
pc->pc_intr_string = necpb_intr_string;
pc->pc_intr_establish = necpb_intr_establish;
pc->pc_intr_disestablish = necpb_intr_disestablish;
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_conf_interrupt = necpb_conf_interrupt;
pc->pc_conf_hook = necpb_conf_hook;
#endif
#ifndef PCI_NETBSD_CONFIGURE
/*
* XXX:
* NEC's firmware does not configure PCI devices completely.
* We need to disable expansion ROM and enable mem/io/busmaster
* bits here.
*/
for (dev = 3; dev <= 5; dev++) {
tag = necpb_make_tag(pc, 0, dev, 0);
id = necpb_conf_read(pc, tag, PCI_ID_REG);
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
class = necpb_conf_read(pc, tag, PCI_CLASS_REG);
csr = necpb_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) {
csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
necpb_conf_write(pc, tag, PCI_MAPREG_ROM, 0);
}
csr |= PCI_COMMAND_MASTER_ENABLE;
necpb_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
}
#endif
ncp->nc_initialized = 1;
}
