static int __init nosmp(char *str) { setup_max_cpus = 0; arch_disable_smp_support(); return 0; }
static int __init maxcpus(char *str) { get_option(&str, &setup_max_cpus); if (setup_max_cpus == 0) arch_disable_smp_support(); return 0; }
void __cpuinit setup_local_APIC(void) { unsigned int value; int i, j; if (disable_apic) { arch_disable_smp_support(); return; } #ifdef CONFIG_X86_32 if (lapic_is_integrated() && apic->disable_esr) { apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0); } #endif perf_events_lapic_init(); preempt_disable(); BUG_ON(!apic->apic_id_registered()); apic->init_apic_ldr(); value = apic_read(APIC_TASKPRI); value &= ~APIC_TPRI_MASK; apic_write(APIC_TASKPRI, value); for (i = APIC_ISR_NR - 1; i >= 0; i--) { value = apic_read(APIC_ISR + i*0x10); for (j = 31; j >= 0; j--) { if (value & (1<<j)) ack_APIC_irq(); } } value = apic_read(APIC_SPIV); value &= ~APIC_VECTOR_MASK; value |= APIC_SPIV_APIC_ENABLED; #ifdef CONFIG_X86_32 value &= ~APIC_SPIV_FOCUS_DISABLED; #endif value |= SPURIOUS_APIC_VECTOR; apic_write(APIC_SPIV, value); value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; if (!smp_processor_id() && (pic_mode || !value)) { value = APIC_DM_EXTINT; apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); } else { value = APIC_DM_EXTINT | APIC_LVT_MASKED; apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); } apic_write(APIC_LVT0, value); if (!smp_processor_id()) value = APIC_DM_NMI; else value = APIC_DM_NMI | APIC_LVT_MASKED; if (!lapic_is_integrated()) value |= APIC_LVT_LEVEL_TRIGGER; apic_write(APIC_LVT1, value); preempt_enable(); #ifdef CONFIG_X86_MCE_INTEL if (smp_processor_id() == 0) cmci_recheck(); #endif }