int __devexit arizona_dev_exit(struct arizona *arizona)
{
mfd_remove_devices(arizona->dev);
arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
pm_runtime_disable(arizona->dev);
arizona_irq_exit(arizona);
return 0;
}
int arizona_dev_exit(struct arizona *arizona)
{
mfd_remove_devices(arizona->dev);
arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
pm_runtime_disable(arizona->dev);
arizona_irq_exit(arizona);
if (arizona->pdata.reset)
gpio_set_value_cansleep(arizona->pdata.reset, 0);
regulator_disable(arizona->dcvdd);
regulator_bulk_disable(ARRAY_SIZE(arizona->core_supplies),
arizona->core_supplies);
return 0;
}
int __devinit arizona_dev_init(struct arizona *arizona)
{
struct device *dev = arizona->dev;
const char *type_name;
unsigned int reg, val;
int (*apply_patch)(struct arizona *) = NULL;
int ret, i;
dev_set_drvdata(arizona->dev, arizona);
mutex_init(&arizona->clk_lock);
if (dev_get_platdata(arizona->dev))
memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
sizeof(arizona->pdata));
regcache_cache_only(arizona->regmap, true);
switch (arizona->type) {
case WM5102:
case WM5110:
for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
arizona->core_supplies[i].supply
= wm5102_core_supplies[i];
arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
break;
default:
dev_err(arizona->dev, "Unknown device type %d\n",
arizona->type);
return -EINVAL;
}
ret = mfd_add_devices(arizona->dev, -1, early_devs,
ARRAY_SIZE(early_devs), NULL, 0);
if (ret != 0) {
dev_err(dev, "Failed to add early children: %d\n", ret);
return ret;
}
ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to request core supplies: %d\n",
ret);
goto err_early;
}
arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
if (IS_ERR(arizona->dcvdd)) {
ret = PTR_ERR(arizona->dcvdd);
dev_err(dev, "Failed to request DCVDD: %d\n", ret);
goto err_early;
}
ret = regulator_bulk_enable(arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n",
ret);
goto err_early;
}
ret = regulator_enable(arizona->dcvdd);
if (ret != 0) {
dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
goto err_enable;
}
if (arizona->pdata.control_init_time)
msleep(arizona->pdata.control_init_time);
if (arizona->pdata.reset) {
/* Start out with /RESET low to put the chip into reset */
ret = gpio_request_one(arizona->pdata.reset,
GPIOF_DIR_OUT | GPIOF_INIT_LOW,
"arizona /RESET");
if (ret != 0) {
dev_err(dev, "Failed to request /RESET: %d\n", ret);
goto err_dcvdd;
}
gpio_set_value_cansleep(arizona->pdata.reset, 1);
}
regcache_cache_only(arizona->regmap, false);
ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
&arizona->rev);
if (ret != 0) {
dev_err(dev, "Failed to read revision register: %d\n", ret);
goto err_reset;
}
arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
switch (reg) {
#ifdef CONFIG_MFD_WM5102
case 0x5102:
type_name = "WM5102";
if (arizona->type != WM5102) {
dev_err(arizona->dev, "WM5102 registered as %d\n",
arizona->type);
arizona->type = WM5102;
}
apply_patch = wm5102_patch;
break;
#endif
#ifdef CONFIG_MFD_WM5110
case 0x5110:
type_name = "WM5110";
if (arizona->type != WM5110) {
dev_err(arizona->dev, "WM5110 registered as %d\n",
arizona->type);
arizona->type = WM5110;
}
apply_patch = wm5110_patch;
break;
#endif
default:
dev_err(arizona->dev, "Unknown device ID %x\n", reg);
goto err_reset;
}
dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
/* If we have a /RESET GPIO we'll already be reset */
if (!arizona->pdata.reset) {
ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
if (ret != 0) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err_reset;
}
}
ret = arizona_wait_for_boot(arizona);
if (ret != 0) {
dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
goto err_reset;
}
if (apply_patch) {
ret = apply_patch(arizona);
if (ret != 0) {
dev_err(arizona->dev, "Failed to apply patch: %d\n",
ret);
goto err_reset;
}
}
for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
if (!arizona->pdata.gpio_defaults[i])
continue;
regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
arizona->pdata.gpio_defaults[i]);
}
pm_runtime_enable(arizona->dev);
/* Chip default */
if (!arizona->pdata.clk32k_src)
arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
case ARIZONA_32KZ_MCLK2:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK,
arizona->pdata.clk32k_src - 1);
break;
case ARIZONA_32KZ_NONE:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK, 2);
break;
default:
dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
arizona->pdata.clk32k_src);
ret = -EINVAL;
goto err_reset;
}
for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
if (!arizona->pdata.micbias[i].mV &&
!arizona->pdata.micbias[i].bypass)
continue;
/* Apply default for bypass mode */
if (!arizona->pdata.micbias[i].mV)
arizona->pdata.micbias[i].mV = 2800;
val = (arizona->pdata.micbias[i].mV - 1500) / 100;
val <<= ARIZONA_MICB1_LVL_SHIFT;
if (arizona->pdata.micbias[i].ext_cap)
val |= ARIZONA_MICB1_EXT_CAP;
if (arizona->pdata.micbias[i].discharge)
val |= ARIZONA_MICB1_DISCH;
if (arizona->pdata.micbias[i].fast_start)
val |= ARIZONA_MICB1_RATE;
if (arizona->pdata.micbias[i].bypass)
val |= ARIZONA_MICB1_BYPASS;
regmap_update_bits(arizona->regmap,
ARIZONA_MIC_BIAS_CTRL_1 + i,
ARIZONA_MICB1_LVL_MASK |
ARIZONA_MICB1_DISCH |
ARIZONA_MICB1_BYPASS |
ARIZONA_MICB1_RATE, val);
}
for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
/* Default for both is 0 so noop with defaults */
val = arizona->pdata.dmic_ref[i]
<< ARIZONA_IN1_DMIC_SUP_SHIFT;
val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
regmap_update_bits(arizona->regmap,
ARIZONA_IN1L_CONTROL + (i * 8),
ARIZONA_IN1_DMIC_SUP_MASK |
ARIZONA_IN1_MODE_MASK, val);
}
for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
/* Default is 0 so noop with defaults */
if (arizona->pdata.out_mono[i])
val = ARIZONA_OUT1_MONO;
else
val = 0;
regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
ARIZONA_OUT1_MONO, val);
}
for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
if (arizona->pdata.spk_mute[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
ARIZONA_SPK1_MUTE_ENDIAN_MASK |
ARIZONA_SPK1_MUTE_SEQ1_MASK,
arizona->pdata.spk_mute[i]);
if (arizona->pdata.spk_fmt[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
ARIZONA_SPK1_FMT_MASK,
arizona->pdata.spk_fmt[i]);
}
/* set virtual IRQs */
arizona->virq[0] = arizona->pdata.irq_base;
arizona->virq[1] = arizona->pdata.irq_base + ARIZONA_NUM_IRQ;
switch (arizona->pdata.mic_spk_clamp) {
case ARIZONA_MIC_CLAMP_SPKLN:
regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_2,
0x3c, 0xc);
break;
case ARIZONA_MIC_CLAMP_SPKLP:
regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_2,
0x3c, 0x1c);
break;
case ARIZONA_MIC_CLAMP_SPKRN:
regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_3,
0x3c, 0xc);
break;
case ARIZONA_MIC_CLAMP_SPKRP:
regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_3,
0x3c, 0x1c);
break;
default:
break;
}
/* Set up for interrupts */
ret = arizona_irq_init(arizona);
if (ret != 0)
goto err_reset;
arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
arizona_clkgen_err, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
arizona_overclocked, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
arizona_underclocked, arizona);
switch (arizona->type) {
case WM5102:
ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
ARRAY_SIZE(wm5102_devs), NULL, 0);
break;
case WM5110:
ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
ARRAY_SIZE(wm5110_devs), NULL, 0);
break;
}
if (ret != 0) {
dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
goto err_irq;
}
if (arizona->pdata.init_done)
arizona->pdata.init_done();
#ifdef CONFIG_PM_RUNTIME
regulator_disable(arizona->dcvdd);
#endif
return 0;
err_irq:
arizona_irq_exit(arizona);
err_reset:
if (arizona->pdata.reset) {
gpio_set_value_cansleep(arizona->pdata.reset, 1);
gpio_free(arizona->pdata.reset);
}
err_dcvdd:
regulator_disable(arizona->dcvdd);
err_enable:
regulator_bulk_disable(arizona->num_core_supplies,
arizona->core_supplies);
err_early:
mfd_remove_devices(dev);
return ret;
}
int arizona_dev_init(struct arizona *arizona)
{
struct device *dev = arizona->dev;
const char *type_name;
unsigned int reg, val;
int (*apply_patch)(struct arizona *) = NULL;
int ret, i;
dev_set_drvdata(arizona->dev, arizona);
mutex_init(&arizona->clk_lock);
if (dev_get_platdata(arizona->dev))
memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
sizeof(arizona->pdata));
else
arizona_of_get_core_pdata(arizona);
regcache_cache_only(arizona->regmap, true);
switch (arizona->type) {
case WM5102:
case WM5110:
case WM8997:
for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
arizona->core_supplies[i].supply
= wm5102_core_supplies[i];
arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
break;
default:
dev_err(arizona->dev, "Unknown device type %d\n",
arizona->type);
return -EINVAL;
}
/* Mark DCVDD as external, LDO1 driver will clear if internal */
arizona->external_dcvdd = true;
ret = mfd_add_devices(arizona->dev, -1, early_devs,
ARRAY_SIZE(early_devs), NULL, 0, NULL);
if (ret != 0) {
dev_err(dev, "Failed to add early children: %d\n", ret);
return ret;
}
ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to request core supplies: %d\n",
ret);
goto err_early;
}
/**
* Don't use devres here because the only device we have to get
* against is the MFD device and DCVDD will likely be supplied by
* one of its children. Meaning that the regulator will be
* destroyed by the time devres calls regulator put.
*/
arizona->dcvdd = regulator_get(arizona->dev, "DCVDD");
if (IS_ERR(arizona->dcvdd)) {
ret = PTR_ERR(arizona->dcvdd);
dev_err(dev, "Failed to request DCVDD: %d\n", ret);
goto err_early;
}
if (arizona->pdata.reset) {
/* Start out with /RESET low to put the chip into reset */
ret = gpio_request_one(arizona->pdata.reset,
GPIOF_DIR_OUT | GPIOF_INIT_LOW,
"arizona /RESET");
if (ret != 0) {
dev_err(dev, "Failed to request /RESET: %d\n", ret);
goto err_dcvdd;
}
}
ret = regulator_bulk_enable(arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n",
ret);
goto err_dcvdd;
}
ret = regulator_enable(arizona->dcvdd);
if (ret != 0) {
dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
goto err_enable;
}
if (arizona->pdata.reset) {
gpio_set_value_cansleep(arizona->pdata.reset, 1);
msleep(1);
}
regcache_cache_only(arizona->regmap, false);
/* Verify that this is a chip we know about */
ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
switch (reg) {
case 0x5102:
case 0x5110:
case 0x8997:
break;
default:
dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
goto err_reset;
}
/* If we have a /RESET GPIO we'll already be reset */
if (!arizona->pdata.reset) {
regcache_mark_dirty(arizona->regmap);
ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
if (ret != 0) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err_reset;
}
msleep(1);
ret = regcache_sync(arizona->regmap);
if (ret != 0) {
dev_err(dev, "Failed to sync device: %d\n", ret);
goto err_reset;
}
}
/* Ensure device startup is complete */
switch (arizona->type) {
case WM5102:
ret = regmap_read(arizona->regmap, 0x19, &val);
if (ret != 0)
dev_err(dev,
"Failed to check write sequencer state: %d\n",
ret);
else if (val & 0x01)
break;
/* Fall through */
default:
ret = arizona_wait_for_boot(arizona);
if (ret != 0) {
dev_err(arizona->dev,
"Device failed initial boot: %d\n", ret);
goto err_reset;
}
break;
}
/* Read the device ID information & do device specific stuff */
ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
&arizona->rev);
if (ret != 0) {
dev_err(dev, "Failed to read revision register: %d\n", ret);
goto err_reset;
}
arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
switch (reg) {
#ifdef CONFIG_MFD_WM5102
case 0x5102:
type_name = "WM5102";
if (arizona->type != WM5102) {
dev_err(arizona->dev, "WM5102 registered as %d\n",
arizona->type);
arizona->type = WM5102;
}
apply_patch = wm5102_patch;
arizona->rev &= 0x7;
break;
#endif
#ifdef CONFIG_MFD_WM5110
case 0x5110:
type_name = "WM5110";
if (arizona->type != WM5110) {
dev_err(arizona->dev, "WM5110 registered as %d\n",
arizona->type);
arizona->type = WM5110;
}
apply_patch = wm5110_patch;
break;
#endif
#ifdef CONFIG_MFD_WM8997
case 0x8997:
type_name = "WM8997";
if (arizona->type != WM8997) {
dev_err(arizona->dev, "WM8997 registered as %d\n",
arizona->type);
arizona->type = WM8997;
}
apply_patch = wm8997_patch;
break;
#endif
default:
dev_err(arizona->dev, "Unknown device ID %x\n", reg);
goto err_reset;
}
dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
if (apply_patch) {
ret = apply_patch(arizona);
if (ret != 0) {
dev_err(arizona->dev, "Failed to apply patch: %d\n",
ret);
goto err_reset;
}
switch (arizona->type) {
case WM5102:
ret = arizona_apply_hardware_patch(arizona);
if (ret != 0) {
dev_err(arizona->dev,
"Failed to apply hardware patch: %d\n",
ret);
goto err_reset;
}
break;
default:
break;
}
}
for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
if (!arizona->pdata.gpio_defaults[i])
continue;
regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
arizona->pdata.gpio_defaults[i]);
}
pm_runtime_set_autosuspend_delay(arizona->dev, 100);
pm_runtime_use_autosuspend(arizona->dev);
pm_runtime_enable(arizona->dev);
/* Chip default */
if (!arizona->pdata.clk32k_src)
arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
case ARIZONA_32KZ_MCLK2:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK,
arizona->pdata.clk32k_src - 1);
arizona_clk32k_enable(arizona);
break;
case ARIZONA_32KZ_NONE:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK, 2);
break;
default:
dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
arizona->pdata.clk32k_src);
ret = -EINVAL;
goto err_reset;
}
for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
if (!arizona->pdata.micbias[i].mV &&
!arizona->pdata.micbias[i].bypass)
continue;
/* Apply default for bypass mode */
if (!arizona->pdata.micbias[i].mV)
arizona->pdata.micbias[i].mV = 2800;
val = (arizona->pdata.micbias[i].mV - 1500) / 100;
val <<= ARIZONA_MICB1_LVL_SHIFT;
if (arizona->pdata.micbias[i].ext_cap)
val |= ARIZONA_MICB1_EXT_CAP;
if (arizona->pdata.micbias[i].discharge)
val |= ARIZONA_MICB1_DISCH;
if (arizona->pdata.micbias[i].soft_start)
val |= ARIZONA_MICB1_RATE;
if (arizona->pdata.micbias[i].bypass)
val |= ARIZONA_MICB1_BYPASS;
regmap_update_bits(arizona->regmap,
ARIZONA_MIC_BIAS_CTRL_1 + i,
ARIZONA_MICB1_LVL_MASK |
ARIZONA_MICB1_DISCH |
ARIZONA_MICB1_BYPASS |
ARIZONA_MICB1_RATE, val);
}
for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
/* Default for both is 0 so noop with defaults */
val = arizona->pdata.dmic_ref[i]
<< ARIZONA_IN1_DMIC_SUP_SHIFT;
val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
regmap_update_bits(arizona->regmap,
ARIZONA_IN1L_CONTROL + (i * 8),
ARIZONA_IN1_DMIC_SUP_MASK |
ARIZONA_IN1_MODE_MASK, val);
}
for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
/* Default is 0 so noop with defaults */
if (arizona->pdata.out_mono[i])
val = ARIZONA_OUT1_MONO;
else
val = 0;
regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
ARIZONA_OUT1_MONO, val);
}
for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
if (arizona->pdata.spk_mute[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
ARIZONA_SPK1_MUTE_ENDIAN_MASK |
ARIZONA_SPK1_MUTE_SEQ1_MASK,
arizona->pdata.spk_mute[i]);
if (arizona->pdata.spk_fmt[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
ARIZONA_SPK1_FMT_MASK,
arizona->pdata.spk_fmt[i]);
}
/* Set up for interrupts */
ret = arizona_irq_init(arizona);
if (ret != 0)
goto err_reset;
arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
arizona_clkgen_err, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
arizona_overclocked, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
arizona_underclocked, arizona);
switch (arizona->type) {
case WM5102:
ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
break;
case WM5110:
ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
break;
case WM8997:
ret = mfd_add_devices(arizona->dev, -1, wm8997_devs,
ARRAY_SIZE(wm8997_devs), NULL, 0, NULL);
break;
}
if (ret != 0) {
dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
goto err_irq;
}
#ifdef CONFIG_PM_RUNTIME
regulator_disable(arizona->dcvdd);
#endif
return 0;
err_irq:
arizona_irq_exit(arizona);
err_reset:
if (arizona->pdata.reset) {
gpio_set_value_cansleep(arizona->pdata.reset, 0);
gpio_free(arizona->pdata.reset);
}
regulator_disable(arizona->dcvdd);
err_enable:
regulator_bulk_disable(arizona->num_core_supplies,
arizona->core_supplies);
err_dcvdd:
regulator_put(arizona->dcvdd);
err_early:
mfd_remove_devices(dev);
return ret;
}
int __devinit arizona_dev_init(struct arizona *arizona)
{
struct device *dev = arizona->dev;
const char *type_name;
unsigned int reg, val;
int ret, i;
dev_set_drvdata(arizona->dev, arizona);
mutex_init(&arizona->clk_lock);
if (dev_get_platdata(arizona->dev))
memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
sizeof(arizona->pdata));
regcache_cache_only(arizona->regmap, true);
switch (arizona->type) {
case WM5102:
case WM5110:
for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
arizona->core_supplies[i].supply
= wm5102_core_supplies[i];
arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
break;
default:
dev_err(arizona->dev, "Unknown device type %d\n",
arizona->type);
return -EINVAL;
}
ret = mfd_add_devices(arizona->dev, -1, early_devs,
ARRAY_SIZE(early_devs), NULL, 0);
if (ret != 0) {
dev_err(dev, "Failed to add early children: %d\n", ret);
return ret;
}
ret = regulator_bulk_get(dev, arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to request core supplies: %d\n",
ret);
goto err_early;
}
ret = regulator_bulk_enable(arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n",
ret);
goto err_bulk_get;
}
if (arizona->pdata.reset) {
/* Start out with /RESET low to put the chip into reset */
ret = gpio_request_one(arizona->pdata.reset,
GPIOF_DIR_OUT | GPIOF_INIT_LOW,
"arizona /RESET");
if (ret != 0) {
dev_err(dev, "Failed to request /RESET: %d\n", ret);
goto err_enable;
}
gpio_set_value_cansleep(arizona->pdata.reset, 1);
}
if (arizona->pdata.ldoena) {
ret = gpio_request_one(arizona->pdata.ldoena,
GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
"arizona LDOENA");
if (ret != 0) {
dev_err(dev, "Failed to request LDOENA: %d\n", ret);
goto err_reset;
}
}
regcache_cache_only(arizona->regmap, false);
ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_ldoena;
}
ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
&arizona->rev);
if (ret != 0) {
dev_err(dev, "Failed to read revision register: %d\n", ret);
goto err_ldoena;
}
arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
switch (reg) {
#ifdef CONFIG_MFD_WM5102
case 0x5102:
type_name = "WM5102";
if (arizona->type != WM5102) {
dev_err(arizona->dev, "WM5102 registered as %d\n",
arizona->type);
arizona->type = WM5102;
}
ret = wm5102_patch(arizona);
break;
#endif
#ifdef CONFIG_MFD_WM5110
case 0x5110:
type_name = "WM5110";
if (arizona->type != WM5110) {
dev_err(arizona->dev, "WM5110 registered as %d\n",
arizona->type);
arizona->type = WM5110;
}
ret = wm5110_patch(arizona);
break;
#endif
default:
dev_err(arizona->dev, "Unknown device ID %x\n", reg);
goto err_ldoena;
}
dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
if (ret != 0)
dev_err(arizona->dev, "Failed to apply patch: %d\n", ret);
/* If we have a /RESET GPIO we'll already be reset */
if (!arizona->pdata.reset) {
ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
if (ret != 0) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err_ldoena;
}
}
ret = arizona_wait_for_boot(arizona);
if (ret != 0) {
dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
goto err_reset;
}
for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
if (!arizona->pdata.gpio_defaults[i])
continue;
regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
arizona->pdata.gpio_defaults[i]);
}
pm_runtime_set_autosuspend_delay(arizona->dev, 100);
pm_runtime_use_autosuspend(arizona->dev);
pm_runtime_enable(arizona->dev);
/* Chip default */
if (!arizona->pdata.clk32k_src)
arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
case ARIZONA_32KZ_MCLK2:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK,
arizona->pdata.clk32k_src - 1);
break;
case ARIZONA_32KZ_NONE:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK, 2);
break;
default:
dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
arizona->pdata.clk32k_src);
ret = -EINVAL;
goto err_ldoena;
}
for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
/* Default for both is 0 so noop with defaults */
val = arizona->pdata.dmic_ref[i]
<< ARIZONA_IN1_DMIC_SUP_SHIFT;
val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
regmap_update_bits(arizona->regmap,
ARIZONA_IN1L_CONTROL + (i * 8),
ARIZONA_IN1_DMIC_SUP_MASK |
ARIZONA_IN1_MODE_MASK, val);
}
for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
/* Default is 0 so noop with defaults */
if (arizona->pdata.out_mono[i])
val = ARIZONA_OUT1_MONO;
else
val = 0;
regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
ARIZONA_OUT1_MONO, val);
}
for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
if (arizona->pdata.spk_mute[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
ARIZONA_SPK1_MUTE_ENDIAN_MASK |
ARIZONA_SPK1_MUTE_SEQ1_MASK,
arizona->pdata.spk_mute[i]);
if (arizona->pdata.spk_fmt[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
ARIZONA_SPK1_FMT_MASK,
arizona->pdata.spk_fmt[i]);
}
/* Set up for interrupts */
ret = arizona_irq_init(arizona);
if (ret != 0)
goto err_ldoena;
arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
arizona_clkgen_err, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
arizona_overclocked, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
arizona_underclocked, arizona);
switch (arizona->type) {
case WM5102:
ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
ARRAY_SIZE(wm5102_devs), NULL, 0);
break;
case WM5110:
ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
ARRAY_SIZE(wm5110_devs), NULL, 0);
break;
}
if (ret != 0) {
dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
goto err_irq;
}
return 0;
err_irq:
arizona_irq_exit(arizona);
err_ldoena:
if (arizona->pdata.ldoena) {
gpio_set_value_cansleep(arizona->pdata.ldoena, 0);
gpio_free(arizona->pdata.ldoena);
}
err_reset:
if (arizona->pdata.reset) {
gpio_set_value_cansleep(arizona->pdata.reset, 1);
gpio_free(arizona->pdata.reset);
}
err_enable:
regulator_bulk_disable(ARRAY_SIZE(arizona->core_supplies),
arizona->core_supplies);
err_bulk_get:
regulator_bulk_free(ARRAY_SIZE(arizona->core_supplies),
arizona->core_supplies);
err_early:
mfd_remove_devices(dev);
return ret;
}
