Ejemplo n.º 1
0
static void
at91_identify(driver_t *drv, device_t parent)
{

	if (at91_cpu_is(AT91_CPU_SAM9260)) {
		at91_add_child(parent, 0, "at91sam9260", 0, 0, 0, -1, 0, 0);
		at91_cpu_add_builtin_children(parent);
	}
}
Ejemplo n.º 2
0
static void
at91_identify(driver_t *drv, device_t parent)
{

	switch (AT91_CPU(at91_chip_id)) {
	case AT91_CPU_SAM9260:
	case AT91_CPU_SAM9XE128:
	case AT91_CPU_SAM9XE256:
	case AT91_CPU_SAM9XE512:
		at91_add_child(parent, 0, "at91sam9260", 0, 0, 0, -1, 0, 0);
		at91_cpu_add_builtin_children(parent);
		break;
	}
}
Ejemplo n.º 3
0
static int
at91_attach(device_t dev)
{
    struct at91_softc *sc = device_get_softc(dev);

    arm_post_filter = at91_eoi;

    at91_softc = sc;
    sc->sc_st = &at91_bs_tag;
    sc->sc_sh = AT91_BASE;
    sc->sc_aic_sh = AT91_BASE + AT91_SYS_BASE;
    sc->dev = dev;

    sc->sc_irq_rman.rm_type = RMAN_ARRAY;
    sc->sc_irq_rman.rm_descr = "AT91 IRQs";
    if (rman_init(&sc->sc_irq_rman) != 0 ||
            rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
        panic("at91_attach: failed to set up IRQ rman");

    sc->sc_mem_rman.rm_type = RMAN_ARRAY;
    sc->sc_mem_rman.rm_descr = "AT91 Memory";
    if (rman_init(&sc->sc_mem_rman) != 0)
        panic("at91_attach: failed to set up memory rman");
    /*
     * Manage the physical space, defined as being everything that isn't
     * DRAM.
     */
    if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0)
        panic("at91_attach: failed to set up memory rman");
    if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20),
                           0xfffffffful) != 0)
        panic("at91_attach: failed to set up memory rman");

    /*
     * Add this device's children...
     */
    at91_cpu_add_builtin_children(dev, soc_info.soc_data->soc_children);
    soc_info.soc_data->soc_clock_init();

    bus_generic_probe(dev);
    bus_generic_attach(dev);
    enable_interrupts(PSR_I | PSR_F);
    return (0);
}
Ejemplo n.º 4
0
static int
at91_attach(device_t dev)
{
	struct at91_softc *sc = device_get_softc(dev);
	int i;

	at91_softc = sc;
	sc->sc_st = &at91_bs_tag;
	sc->sc_sh = AT91RM92_BASE;
	sc->dev = dev;
	if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE,
	    AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0)
		panic("Enable to map IRQ registers");
	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
	sc->sc_irq_rman.rm_descr = "AT91 IRQs";
	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
	sc->sc_mem_rman.rm_descr = "AT91 Memory";
#if 0
	sc->sc_usbmem_rman.rm_type = RMAN_ARRAY;
	sc->sc_usbmem_rman.rm_descr = "AT91RM9200 USB Memory-mapped regs";
#endif
	if (rman_init(&sc->sc_irq_rman) != 0 ||
	    rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
		panic("at91_attach: failed to set up IRQ rman");
	if (rman_init(&sc->sc_mem_rman) != 0 ||
	    rman_manage_region(&sc->sc_mem_rman, 0xdff00000ul,
	    0xdffffffful) != 0)
		panic("at91_attach: failed to set up memory rman");
	if (rman_manage_region(&sc->sc_mem_rman, AT91RM92_OHCI_BASE,
	    AT91RM92_OHCI_BASE + AT91RM92_OHCI_SIZE - 1) != 0)
		panic("at91_attach: failed to set up ohci memory");

	for (i = 0; i < 32; i++) {
		bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SVR + 
		    i * 4, i);
		/* Priority. */
		bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SMR + i * 4,
		    irq_prio[i]);
		if (i < 8)
			bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_EOICR,
			    1);
	}
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SPU, 32);
	/* No debug. */
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_DCR, 0);
	/* Disable and clear all interrupts. */
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_IDCR, 0xffffffff);
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_ICCR, 0xffffffff);

	/* XXX */
	/* Disable all interrupts for RTC (0xe24 == RTC_IDR) */
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff);
	/* DIsable all interrupts for DBGU */
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x20c, 0xffffffff);
	/* Disable all interrupts for the SDRAM controller */
	bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff);

	at91_cpu_add_builtin_children(dev, sc);

	bus_generic_probe(dev);
	bus_generic_attach(dev);
	enable_interrupts(I32_bit | F32_bit);
	return (0);
}
Ejemplo n.º 5
0
static int
at91_attach(device_t dev)
{
	struct at91_softc *sc = device_get_softc(dev);
	int i;

	arm_post_filter = at91_eoi;

	at91_softc = sc;
	sc->sc_st = &at91_bs_tag;
	sc->sc_sh = AT91_BASE;
	sc->sc_aic_sh = AT91_BASE + AT91_SYS_BASE;
	sc->dev = dev;

	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
	sc->sc_irq_rman.rm_descr = "AT91 IRQs";
	if (rman_init(&sc->sc_irq_rman) != 0 ||
	    rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
		panic("at91_attach: failed to set up IRQ rman");

	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
	sc->sc_mem_rman.rm_descr = "AT91 Memory";
	if (rman_init(&sc->sc_mem_rman) != 0)
		panic("at91_attach: failed to set up memory rman");
	/*
	 * Manage the physical space, defined as being everything that isn't
	 * DRAM.
	 */
	if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0)
		panic("at91_attach: failed to set up memory rman");
	if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20),
	    0xfffffffful) != 0)
		panic("at91_attach: failed to set up memory rman");

	/*
	 * Setup the interrupt table.
	 */
	if (soc_info.soc_data == NULL || soc_info.soc_data->soc_irq_prio == NULL)
		panic("Interrupt priority table missing\n");
	for (i = 0; i < 32; i++) {
		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR +
		    i * 4, i);
		/* Priority. */
		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4,
		    soc_info.soc_data->soc_irq_prio[i]);
		if (i < 8)
			bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR,
			    1);
	}

	bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32);
	/* No debug. */
	bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0);
	/* Disable and clear all interrupts. */
	bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
	bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);

        /*
         * Add this device's children...
         */
	at91_cpu_add_builtin_children(dev, soc_info.soc_data->soc_children);
	soc_info.soc_data->soc_clock_init();

	bus_generic_probe(dev);
	bus_generic_attach(dev);
	enable_interrupts(I32_bit | F32_bit);
	return (0);
}