static void __init common_setup(bool pcie_slot)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&archer_c7_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
archer_c7_leds_gpio);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
if (pcie_slot) {
ath79_register_pci();
} else {
ath79_init_mac(tmpmac, mac, -1);
ap9x_pci_setup_wmac_led_pin(0, 0);
ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac);
}
mdiobus_register_board_info(archer_c7_mdio0_info,
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
static void __init wdr7500_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(&wdr7500_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr7500_leds_gpio),
wdr7500_leds_gpio);
ath79_register_gpio_keys_polled(-1, WDR7500_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wdr7500_gpio_keys),
wdr7500_gpio_keys);
gpio_request_one(WDR7500_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(WDR7500_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
ath79_register_nfc();
ath79_register_wmac(art + WDR7500_WMAC_CALDATA_OFFSET, NULL);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WDR7500_MAC0_OFFSET, 0);
mdiobus_register_board_info(wdr7500_mdio0_info,
ARRAY_SIZE(wdr7500_mdio0_info));
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init archer_c60_v1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f010008);
u8 *art = (u8 *) KSEG1ADDR(0x1f7f0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c60_v1_leds_gpio),
archer_c60_v1_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C60_V1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c60_v1_gpio_keys),
archer_c60_v1_gpio_keys);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C60_V1_WMAC_CALDATA_OFFSET, mac);
ap91_pci_init(art + ARCHER_C60_V1_PCI_CALDATA_OFFSET, NULL);
}
static void __init wpj342_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio),
wpj342_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpj342_gpio_keys),
wpj342_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(wpj342_mdio0_info,
ARRAY_SIZE(wpj342_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0);
/* GMAC0 is connected to an AR8236 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init archer_c7_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&archer_c7_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
archer_c7_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c7_gpio_keys),
archer_c7_gpio_keys);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
ath79_register_pci();
mdiobus_register_board_info(archer_c7_mdio0_info,
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
archer_c7_gmac_setup();
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
static void __init common_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
/*
* ath79_eth0 would be the WAN port, but is not connected.
* ath79_eth1 connects to the internal switch chip, however
* we have a single LAN port only.
*/
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_m25p80(&tl_wa901nd_flash_data);
}
static void __init mynet_rext_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(MYNET_REXT_ART_ADDR);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&mynet_rext_flash_data);
/* GPIO configuration from drivers/char/GPIO8.c */
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_POWER,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_WIFI,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY1,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY2,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY3,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_ETHERNET,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_rext_leds_gpio),
mynet_rext_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_REXT_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_rext_gpio_keys),
mynet_rext_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_RXD_DELAY |
AR934X_ETH_CFG_RDV_DELAY);
ath79_register_mdio(0, 0x0);
/* LAN */
mynet_rext_get_mac("et0macaddr=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to an external PHY on Port 4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x0e000000; /* athrs_mac.c */
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* WLAN */
mynet_rext_get_mac("wl0_hwaddr=", tmpmac);
ap91_pci_init(art + MYNET_REXT_WMAC_CALDATA_OFFSET, tmpmac);
}
static void __init tew673gru_setup(void)
{
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
tew673gru_read_ascii_mac(mac1, TEW673GRU_MAC_LOCATION_0);
tew673gru_read_ascii_mac(mac2, TEW673GRU_MAC_LOCATION_1);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
ath79_eth0_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_pll_data.pll_1000 = 0x11110000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
ath79_eth1_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = 0x10;
ath79_eth1_pll_data.pll_1000 = 0x11110000;
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tew673gru_leds_gpio),
tew673gru_leds_gpio);
ath79_register_gpio_keys_polled(-1, TEW673GRU_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tew673gru_gpio_keys),
tew673gru_gpio_keys);
ath79_register_usb();
platform_device_register(&tew673gru_rtl8366s_device);
ap9x_pci_setup_wmac_led_pin(0, 5);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap94_pci_init((u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_0), mac1,
(u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_1), mac2);
spi_register_board_info(tew673gru_spi_info,
ARRAY_SIZE(tew673gru_spi_info));
platform_device_register(&tew673gru_spi_device);
}
static void __init wdr4300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wdr4300_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio),
wdr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wdr4300_gpio_keys),
wdr4300_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 0);
ap9x_pci_setup_wmac_led_pin(0, 0);
ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wdr4300_mdio0_info,
ARRAY_SIZE(wdr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
gpio_request_one(WDR4300_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(WDR4300_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
/*
* Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
* The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
* assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
* SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
* The SFP cage is not assigned by default on RouterOS. Extra work is required
* to support this interface as it is directly connected to the SoC (eth1).
* Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
* attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
* they are not attached to GPIOs, extra work is required to support these.
* PoE and USB output power control is supported.
*/
static void __init rb962_setup(void)
{
u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI;
if (!rbspi_platform_setup())
return;
rbspi_peripherals_setup(flags);
/* Do not call rbspi_network_setup as we have a discrete switch chip */
ath79_eth0_pll_data.pll_1000 = 0xae000000;
ath79_eth0_pll_data.pll_100 = 0xa0000101;
ath79_eth0_pll_data.pll_10 = 0xa0001313;
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(rb962_mdio0_info,
ARRAY_SIZE(rb962_mdio0_info));
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* WLAN1 MAC is HW MAC + 7 */
rbspi_wlan_init(1, 7);
if (flags & RBSPI_HAS_USB)
gpio_request_one(RB962_GPIO_USB_PWROFF, GPIOF_ACTIVE_LOW |
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power off");
/* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
if (flags & RBSPI_HAS_POE)
gpio_request_one(RB962_GPIO_POE_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
GPIOF_EXPORT_DIR_FIXED,
"POE power");
ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio),
rb962_leds_gpio);
/* This device has a single reset button as gpio 20 */
rbspi_register_reset_button(RB962_GPIO_BTN_RESET);
}
static void __init rb922gs_setup(void)
{
const struct rb_info *info;
char buf[64];
info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000);
if (!info)
return;
scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s",
(info->board_name) ? info->board_name : "");
mips_set_machine_name(buf);
rb922gs_init_partitions(info);
ath79_register_m25p80(&rb922gs_spi_flash_data);
rb922gs_nand_init();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(rb922gs_mdio0_info,
ARRAY_SIZE(rb922gs_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR);
ath79_eth0_pll_data.pll_10 = 0x81001313;
ath79_eth0_pll_data.pll_100 = 0x81000101;
ath79_eth0_pll_data.pll_1000 = 0x8f000000;
ath79_register_eth(0);
ath79_register_pci();
ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds);
ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL,
ARRAY_SIZE(rb922gs_gpio_keys),
rb922gs_gpio_keys);
/* NOTE:
* This only supports the RB911G-5HPacD board for now. For other boards
* more devices must be registered based on the hardware options which
* can be found in the hardware configuration of RouterBOOT.
*/
}
static void __init dir825c1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET);
dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET);
ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
dir825c1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825c1_gpio_keys),
dir825c1_gpio_keys);
ap9x_pci_setup_wmac_led_pin(0, 13);
ap9x_pci_setup_wmac_led_pin(1, 32);
ath79_init_mac(tmpmac, mac1, 0);
ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac2, 0);
ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(dir825c1_mdio0_info,
ARRAY_SIZE(dir825c1_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init wzrhpag300h_setup(void)
{
u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000);
u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000);
u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET;
u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET;
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1);
ath79_register_mdio(0, ~(BIT(0) | BIT(4)));
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = BIT(4);
ath79_register_eth(0);
ath79_register_eth(1);
gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio),
wzrhpag300h_leds_gpio);
ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wzrhpag300h_gpio_keys),
wzrhpag300h_gpio_keys);
ath79_register_m25p80_multi(&wzrhpag300h_flash_data);
ap94_pci_init(eeprom1, mac1, eeprom2, mac2);
ap9x_pci_setup_wmac_led_pin(0, 1);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio,
ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio));
ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio,
ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio));
}
static void __init dw33d_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio),
dw33d_leds_gpio);
ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dw33d_gpio_keys),
dw33d_gpio_keys);
ath79_register_usb();
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_pci();
ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0);
mdiobus_register_board_info(dw33d_mdio0_info,
ARRAY_SIZE(dw33d_mdio0_info));
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_register_eth(0);
/* GMAC1 is connected tot eh SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_register_eth(1);
}
static void __init om2p_hs_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
/* enable reset button */
ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
ath79_register_m25p80(&om2p_lc_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_register_wmac(art, NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
}
static void __init mynet_n750_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio),
mynet_n750_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_n750_gpio_keys),
mynet_n750_gpio_keys);
/*
* Control signal for external LNAs 0 and 1
* Taken from GPL bootloader source:
* board/ar7240/db12x/alpha_gpio.c
*/
ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1);
mynet_n750_get_mac("wlan24mac=", tmpmac);
ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac);
mynet_n750_get_mac("wlan5mac=", tmpmac);
ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(mynet_n750_mdio0_info,
ARRAY_SIZE(mynet_n750_mdio0_info));
ath79_mdio0_data.reset = mynet_n750_mdio_fixup;
ath79_register_mdio(0, 0x0);
mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init dir825b1_setup(void)
{
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
dir825b1_read_ascii_mac(mac1, DIR825B1_MAC_LOCATION_0);
dir825b1_read_ascii_mac(mac2, DIR825B1_MAC_LOCATION_1);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_pll_data.pll_1000 = 0x11110000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = 0x10;
ath79_eth1_pll_data.pll_1000 = 0x11110000;
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_m25p80(&dir825b1_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
dir825b1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825b1_gpio_keys),
dir825b1_gpio_keys);
ath79_register_usb();
platform_device_register(&dir825b1_rtl8366s_device);
ap9x_pci_setup_wmac_led_pin(0, 5);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), mac1,
(u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), mac2);
}
static void __init mr900_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6], pcie_mac[6];
struct ath9k_platform_data *pdata;
ath79_eth0_pll_data.pll_1000 = 0xae000000;
ath79_eth0_pll_data.pll_100 = 0xa0000101;
ath79_eth0_pll_data.pll_10 = 0xa0001313;
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio),
mr900_leds_gpio);
ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mr900_gpio_keys),
mr900_gpio_keys);
ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1);
ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac);
ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16);
ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac);
pdata = ap9x_pci_get_wmac_data(0);
if (!pdata) {
pr_err("mr900: unable to get address of wlan data\n");
return;
}
pdata->use_eeprom = true;
mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr900_mdio0_info,
ARRAY_SIZE(mr900_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(5);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
}
static void __init tl_wr1043nd_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
ath79_register_m25p80(&wr1043nd_v2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio),
tl_wr1043_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr1043_v2_gpio_keys),
tl_wr1043_v2_gpio_keys);
tplink_register_builtin_wmac1(TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac, -1);
mdiobus_register_board_info(wr1043nd_v2_mdio0_info,
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
ath79_register_eth(1);
ath79_register_usb();
gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
}
static void __init om2p_lc_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
u32 t;
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
ath79_register_m25p80(&om2p_lc_flash_data);
om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER;
om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED;
om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW;
om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN;
om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN;
om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN;
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET;
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(art, NULL);
}
static void __init rb95x_setup(void)
{
rb95x_gpio_init();
rb95x_nand_init();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(rb95x_mdio0_info,
ARRAY_SIZE(rb95x_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
}
static void __init tl_wr841n_v8_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
tl_wr841n_v8_leds_gpio);
ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
tl_wr841n_v8_gpio_keys);
/* enable power for the USB port */
gpio_request(TL_WR841NV8_GPIO_USB_POWER, "USB power");
gpio_direction_input(TL_WR841NV8_GPIO_USB_POWER);
ath79_register_usb();
/* END for the USB port */
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init dir_600_a1_setup(void)
{
const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
u8 mac_buff[6];
u8 *mac = NULL;
if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE,
"lan_mac=", mac_buff) == 0) {
ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1);
mac = mac_buff;
}
ath79_register_m25p80(NULL);
ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio),
dir_600_a1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir_600_a1_gpio_keys),
dir_600_a1_gpio_keys);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
ath79_register_mdio(0, 0x0);
/* LAN ports */
ath79_register_eth(1);
/* WAN port */
ath79_register_eth(0);
ap91_pci_init(ee, mac);
}
static void __init cf_e380ac_v1v2_common_setup(unsigned long art_ofs)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f000000 + art_ofs);
cf_exxxn_common_setup(art_ofs, CF_E380AC_V1V2_GPIO_EXT_WDT);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(cf_e380ac_v1v2_mdio0_info,
ARRAY_SIZE(cf_e380ac_v1v2_mdio0_info));
/* LAN */
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_pll_data.pll_1000 = 0xbe000000;
ath79_eth0_pll_data.pll_100 = 0xb0000101;
ath79_eth0_pll_data.pll_10 = 0xb0001313;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
ap91_pci_init(mac + 0x5000, NULL);
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_WLAN2G, true);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_WLAN5G, true);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_WLAN5G, 0);
/* For J7-4 */
ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e380ac_v1v2_gpio_keys),
cf_e380ac_v1v2_gpio_keys);
}
static void __init gl_ar300m_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_spi(&gl_ar300m_spi_data, gl_ar300m_spi_info, 2);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar300m_leds_gpio),
gl_ar300m_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_AR300M_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_ar300m_gpio_keys),
gl_ar300m_gpio_keys);
ath79_register_mdio(0, 0x0);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art + GL_AR300M_MAC0_OFFSET, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, art + GL_AR300M_MAC1_OFFSET, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_init_mac(tmpmac, art + GL_AR300M_WMAC_CALDATA_OFFSET + 2, 0);
ath79_register_wmac(art + GL_AR300M_WMAC_CALDATA_OFFSET, tmpmac);
/* enable usb */
ath79_register_usb();
/* enable pci */
ath79_register_pci();
}
static void __init tew_732br_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(TEW_732BR_ART_ADDRESS);
u8 lan_mac[ETH_ALEN];
u8 wan_mac[ETH_ALEN];
ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_732br_leds_gpio),
tew_732br_leds_gpio);
ath79_register_gpio_keys_polled(1, TEW_732BR_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tew_732br_gpio_keys),
tew_732br_gpio_keys);
ath79_register_m25p80(NULL);
ath79_parse_ascii_mac(art + TEW_732BR_LAN_MAC_OFFSET, lan_mac);
ath79_parse_ascii_mac(art + TEW_732BR_WAN_MAC_OFFSET, wan_mac);
ath79_register_wmac(art + TEW_732BR_CALDATA_OFFSET, lan_mac);
ath79_register_mdio(1, 0x0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
/* LAN: GMAC1 is connected to the internal switch */
ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN: GMAC0 is connected to the PHY4 of the internal switch */
ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
}
static void __init wzr_450hp2_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac_wan = art;
u8 *mac_lan = mac_wan + ETH_ALEN;
ath79_register_m25p80(&wzr_450hp2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wzr_450hp2_leds_gpio),
wzr_450hp2_leds_gpio);
ath79_register_gpio_keys_polled(-1, WZR_450HP2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wzr_450hp2_gpio_keys),
wzr_450hp2_gpio_keys);
ath79_register_wmac(art + WZR_450HP2_WMAC_CALDATA_OFFSET, mac_lan);
mdiobus_register_board_info(wzr_450hp2_mdio0_info,
ARRAY_SIZE(wzr_450hp2_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac_wan, 0);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac_lan, 0);
ath79_register_eth(1);
ath79_register_usb();
}
static void __init tl_ap123_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(&tl_wax50re_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
static void __init sc1750_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(sc1750_leds_gpio),
sc1750_leds_gpio);
ath79_register_gpio_keys_polled(-1, SC1750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(sc1750_gpio_keys),
sc1750_gpio_keys);
ath79_register_usb();
ath79_register_nfc();
ath79_register_wmac(art + SC1750_WMAC_CALDATA_OFFSET, NULL);
ath79_register_mdio(0, 0);
mdiobus_register_board_info(sc1750_mdio0_info,
ARRAY_SIZE(sc1750_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + SC1750_MAC0_OFFSET, 0);
ath79_eth0_pll_data.pll_1000 = 0xa6000101;
ath79_eth0_pll_data.pll_100 = 0xa4000101;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = 0xF;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init ubnt_xm_init(void)
{
u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
ubnt_xm_leds_gpio);
ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ubnt_xm_gpio_keys),
ubnt_xm_gpio_keys);
ath79_register_m25p80(NULL);
ap91_pci_init(eeprom, NULL);
ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_eth(0);
}
