/**
* @brief send data to axi dma thread.
*
* @param[in] temp user parameters
* @retval NULL
*
*/
void *thread_dac_func_single(void* temp)
{
pthread_detach(pthread_self());
cpu_set_t mask ;
CPU_ZERO(&mask);
CPU_SET(0,&mask);
int ret = 0, i = 0, length = 0, times = 0;
int dac_mode = (~cycle_mode)&0x01;
ret =pthread_setaffinity_np(pthread_self(),sizeof(mask),(const cpu_set_t*)&mask );
if(ret < 0)
printf("dac:pthread_setaffinity_np error... \n");
do
{
#if 0
if(file_length < 20*1024*1024) {
axi_dma_init(MM2S_CHANNEL, 2048, file_length/2048-1, MM2S_SRC_ADDR, (unsigned long)dma_reg_addr_rd);
axi_dma_start(MM2S_CHANNEL, 0, (unsigned long)dma_reg_addr_rd);
//check_dma_done(MM2S_CHANNEL, (unsigned long)dma_reg_addr_rd);
}
#endif
if(file_length < LENGTH_MAX){
for(i = file_length; i>=8; i-=8) {
if(file_length%i==0) {
length = i;
times = file_length/i;
dma_dbg(MSG_DEBUG,"file_length = %d, length = %d, times = %d\n", file_length, length, times);
break;
}
}
} else {
for(i = LENGTH_MAX; i>=8; i-=8) {
if(file_length%i==0) {
length = i;
times = file_length/i;
dma_dbg(MSG_DEBUG,"file_length = %d, length = %d, times = %d\n", file_length, length, times);
break;
}
}
}
axi_dma_init(MM2S_CHANNEL, length, times-1, MM2S_SRC_ADDR, (unsigned long)dma_reg_addr_rd);
axi_dma_start(MM2S_CHANNEL, dac_mode, (unsigned long)dma_reg_addr_rd);
if(dac_mode == 1){
check_dma_done(MM2S_CHANNEL, (unsigned long)dma_reg_addr_rd);
axi_dma_reset(MM2S_CHANNEL, (unsigned long)dma_reg_addr_rd, FIFO_IP_RESET);
}
}while(0);
return NULL;
}
void nap_setup(void)
{
nap_rd_dna(nap_dna);
/* TODO: Call nap_unlock with valid key */
nap_track_n_channels = (NAP->STATUS & NAP_STATUS_TRACKING_CH_Msk) >>
NAP_STATUS_TRACKING_CH_Pos;
nap_track_n_channels = MIN(nap_track_n_channels, NAP_MAX_N_TRACK_CHANNELS);
axi_dma_init();
axi_dma_start(&AXIDMADriver1);
/* NAP_FE10_PINC initialization for GPS L1C/A processing */
NAP->FE_PINC[0] = NAP_FE_L1CA_BASEBAND_MIXER_PINC;
/* NAP_FE40_PINC initialization for GPS L2C processing */
NAP->FE_PINC[6] = NAP_FE_L2C_BASEBAND_MIXER_PINC;
/* Enable NAP interrupt */
chThdCreateStatic(wa_nap_exti, sizeof(wa_nap_exti), HIGHPRIO-1, nap_exti_thread, NULL);
gic_handler_register(IRQ_ID_NAP_TRACK, nap_isr, NULL);
gic_irq_sensitivity_set(IRQ_ID_NAP_TRACK, IRQ_SENSITIVITY_EDGE);
gic_irq_priority_set(IRQ_ID_NAP_TRACK, NAP_IRQ_PRIORITY);
gic_irq_enable(IRQ_ID_NAP_TRACK);
}
/**
* @brief recv data from axi dma ipcore thread.
*
* @param[in] temp user parameters
* @retval NULL
*
*/
void *thread_adc_func(void* temp)
{
pthread_detach(pthread_self());
cpu_set_t mask ;
CPU_ZERO(&mask);
CPU_SET(2,&mask);
int ret = 0;
ret =pthread_setaffinity_np(pthread_self(),sizeof(mask),(const cpu_set_t*)&mask );
if(ret < 0)
printf("dac:pthread_setaffinity_np error... \n");
do
{
if(rx_length%LENGTH_MAX != 0 && rx_length%8==0 && rx_length < 20*1024*1024) {
if(rx_length < LENGTH_MAX) {
axi_dma_init(S2MM_CHANNEL, rx_length, 0, S2MM_DST_ADDR,
(unsigned long)dma_reg_addr_wr);
axi_dma_start(S2MM_CHANNEL, 0, (unsigned long)dma_reg_addr_wr);
check_dma_done(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr);
axi_dma_reset(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr, IP_RESET);
} else {
axi_dma_init(S2MM_CHANNEL, LENGTH_MAX, rx_length/LENGTH_MAX-1, S2MM_DST_ADDR,
(unsigned long)dma_reg_addr_wr);
axi_dma_start(S2MM_CHANNEL, 0, (unsigned long)dma_reg_addr_wr);
check_dma_done(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr);
axi_dma_reset(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr, IP_RESET);
axi_dma_init(S2MM_CHANNEL, rx_length%LENGTH_MAX, 0, S2MM_DST_ADDR + (rx_length - rx_length%LENGTH_MAX),
(unsigned long)dma_reg_addr_wr);
axi_dma_start(S2MM_CHANNEL, 0, (unsigned long)dma_reg_addr_wr);
check_dma_done(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr);
}
}else if(rx_length%LENGTH_MAX == 0 && rx_length < 20*1024*1024) {
axi_dma_init(S2MM_CHANNEL, LENGTH_MAX, rx_length/LENGTH_MAX-1, S2MM_DST_ADDR,
(unsigned long)dma_reg_addr_wr);
axi_dma_start(S2MM_CHANNEL, 0, (unsigned long)dma_reg_addr_wr);
check_dma_done(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr);
}
else
dma_dbg(MSG_DEBUG,"Invalid argument!\n");
if(send(connfd, (void *)adc_mem_addr, rx_length, 0)<0)
dma_dbg(MSG_DEBUG,"send:errno=%s\n", strerror(errno));
axi_dma_reset(S2MM_CHANNEL, (unsigned long)dma_reg_addr_wr, FIFO_IP_RESET);
}while(0);
return NULL;
}
/**
* @brief continuous data transmission to axi dma thread.
*
* @param[in] temp user parameters
* @retval NULL
*
*/
void *thread_dac_func_cycle(void* temp)
{
pthread_detach(pthread_self());
cpu_set_t mask ;
CPU_ZERO(&mask);
CPU_SET(0,&mask);
int ret = 0;
ret =pthread_setaffinity_np(pthread_self(),sizeof(mask),(const cpu_set_t*)&mask );
if(ret < 0)
printf("dac:pthread_setaffinity_np error... \n");
while(1)
{
//pthread_mutex_lock(&lock);
if(p->front==p->rear)
{
dma_dbg(MSG_WARNING,"queue empty!\n");
//pthread_mutex_unlock(&lock);
continue;
}
else
{
dma_dbg(MSG_WARNING,"buffer is not empty!\n");
//pthread_mutex_unlock(&lock);
p->front=(p->front+1)%MaxSize;
do
{
axi_dma_init(MM2S_CHANNEL, 2048, BUFFER_MAX_SIZE/2048, MM2S_SRC_ADDR+(p->data[p->front]-dac_mem_addr), (unsigned long)dma_reg_addr_rd);
axi_dma_start(MM2S_CHANNEL, 1, (unsigned long)dma_reg_addr_rd);
check_dma_done(MM2S_CHANNEL, (unsigned long)dma_reg_addr_rd);
axi_dma_reset(MM2S_CHANNEL, (unsigned long)dma_reg_addr_rd, FIFO_IP_RESET);
}while(0);
}
}
return NULL;
}
static int axiemac_init(struct eth_device *dev, bd_t * bis)
{
struct axidma_priv *priv = dev->priv;
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 temp;
debug("axiemac: Init started\n");
/*
* Initialize AXIDMA engine. AXIDMA engine must be initialized before
* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
axi_dma_init(dev);
/* Initialize AxiEthernet hardware. */
if (axi_ethernet_init(dev))
return -1;
/* Disable all RX interrupts before RxBD space setup */
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
out_be32(&priv->dmarx->control, temp);
/* Start DMA RX channel. Now it's ready to receive data.*/
out_be32(&priv->dmarx->current, (u32)&rx_bd);
/* Setup the BD. */
memset(&rx_bd, 0, sizeof(rx_bd));
rx_bd.next = (u32)&rx_bd;
rx_bd.phys = (u32)&rxframe;
rx_bd.cntrl = sizeof(rxframe);
/* Flush the last BD so DMA core could see the updates */
flush_cache((u32)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache can contain uninitialized data */
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Start the hardware */
temp = in_be32(&priv->dmarx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
out_be32(&priv->dmarx->control, temp);
/* Rx BD is ready - start */
out_be32(&priv->dmarx->tail, (u32)&rx_bd);
/* Enable TX */
out_be32(®s->tc, XAE_TC_TX_MASK);
/* Enable RX */
out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
/* PHY setup */
if (!setup_phy(dev)) {
axiemac_halt(dev);
return -1;
}
debug("axiemac: Init complete\n");
return 0;
}