void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
u16 offset, u32 value)
{
b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
b43_phy_write(dev, B43_PHY_OTABLEI, value);
b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16));
}
static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
{
struct b43_phy_ht *phy_ht = dev->phy.ht;
static const u16 base[] = { 0x840, 0x860, 0x880 };
u16 save_regs[3][3];
s32 rssi_buf[6];
int core;
for (core = 0; core < 3; core++) {
save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
b43_phy_write(dev, base[core] + 6, 0);
b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
b43_phy_set(dev, base[core] + 0, 0x0400);
b43_phy_set(dev, base[core] + 0, 0x1000);
}
b43_phy_ht_tx_tone(dev);
udelay(20);
b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
b43_phy_ht_stop_playback(dev);
b43_phy_ht_reset_cca(dev);
phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
for (core = 0; core < 3; core++) {
b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
}
}
u32 b43_lcntab_read(struct b43_wldev *dev, u32 offset)
{
u32 type, value;
type = offset & B43_LCNTAB_TYPEMASK;
offset &= ~B43_LCNTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
switch (type) {
case B43_LCNTAB_8BIT:
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO) & 0xFF;
break;
case B43_LCNTAB_16BIT:
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO);
break;
case B43_LCNTAB_32BIT:
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO);
value |= (b43_phy_read(dev, B43_PHY_LCN_TABLE_DATAHI) << 16);
break;
default:
B43_WARN_ON(1);
value = 0;
}
return value;
}
static void b43_wa_boards_g(struct b43_wldev *dev)
{
struct ssb_sprom *sprom = dev->dev->bus_sprom;
struct b43_phy *phy = &dev->phy;
if (dev->dev->board_vendor != SSB_BOARDVENDOR_BCM ||
dev->dev->board_type != SSB_BOARD_BU4306 ||
dev->dev->board_rev != 0x17) {
if (phy->rev < 2) {
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
} else {
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
if ((sprom->boardflags_lo & B43_BFL_EXTLNA) &&
(phy->rev >= 7)) {
b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
}
}
}
if (sprom->boardflags_lo & B43_BFL_FEM) {
b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
}
}
static void b43_wa_boards_a(struct b43_wldev *dev)
{
if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM &&
dev->dev->board_type == SSB_BOARD_BU4306 &&
dev->dev->board_rev < 0x30) {
b43_phy_write(dev, 0x0010, 0xE000);
b43_phy_write(dev, 0x0013, 0x0140);
b43_phy_write(dev, 0x0014, 0x0280);
} else {
if (dev->dev->board_type == SSB_BOARD_MP4318 &&
dev->dev->board_rev < 0x20) {
b43_phy_write(dev, 0x0013, 0x0210);
b43_phy_write(dev, 0x0014, 0x0840);
} else {
b43_phy_write(dev, 0x0013, 0x0140);
b43_phy_write(dev, 0x0014, 0x0280);
}
if (dev->phy.rev <= 4)
b43_phy_write(dev, 0x0010, 0xE000);
else
b43_phy_write(dev, 0x0010, 0x2000);
b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
}
}
static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
{
u16 bbcfg;
b43_phy_force_clock(dev, true);
bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
udelay(1);
b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
b43_phy_force_clock(dev, false);
b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
}
static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
{
u8 i, j;
u16 base[] = { 0x40, 0x60, 0x80 };
for (i = 0; i < ARRAY_SIZE(base); i++) {
for (j = 0; j < 4; j++)
b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
}
for (i = 0; i < ARRAY_SIZE(base); i++)
b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
}
static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
{
int i;
u16 len = 20 << 3;
b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
for (i = 0; i < len; i++) {
b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
}
return len;
}
/* wlc_lcnphy_bu_tweaks */
static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
{
b43_phy_set(dev, 0x805, 0x1);
b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
b43_phy_write(dev, 0x414, 0x1e10);
b43_phy_write(dev, 0x415, 0x0640);
b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
b43_phy_set(dev, 0x44a, 0x44);
b43_phy_write(dev, 0x44a, 0x80);
b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
if (dev->dev->bus_sprom->board_rev >= 0x1204)
b43_radio_set(dev, 0x09b, 0xf0);
b43_phy_write(dev, 0x7d6, 0x0902);
b43_phy_maskset(dev, 0x429, ~0xf, 0x9);
b43_phy_maskset(dev, 0x429, ~(0x3f << 4), 0xe << 4);
if (dev->phy.rev == 1) {
b43_phy_maskset(dev, 0x423, ~0xff, 0x46);
b43_phy_maskset(dev, 0x411, ~0xff, 1);
b43_phy_set(dev, 0x434, 0xff); /* FIXME: update to wl */
/* TODO: wl operates on PHY 0x416, brcmsmac is outdated here */
b43_phy_maskset(dev, 0x656, ~0xf, 2);
b43_phy_set(dev, 0x44d, 4);
b43_radio_set(dev, 0x0f7, 0x4);
b43_radio_mask(dev, 0x0f1, ~0x3);
b43_radio_maskset(dev, 0x0f2, ~0xf8, 0x90);
b43_radio_maskset(dev, 0x0f3, ~0x3, 0x2);
b43_radio_maskset(dev, 0x0f3, ~0xf0, 0xa0);
b43_radio_set(dev, 0x11f, 0x2);
b43_phy_lcn_clear_tx_power_offsets(dev);
/* TODO: something more? */
}
}
u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset)
{
assert_sizes();
b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
return b43_phy_read(dev, B43_PHY_OTABLEI);
}
void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
u16 offset, u16 value)
{
struct b43_phy_g *gphy = dev->phy.g;
u16 addr;
addr = table + offset;
if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) ||
(addr - 1 != gphy->ofdmtab_addr)) {
b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE;
}
gphy->ofdmtab_addr = addr;
b43_phy_write(dev, B43_PHY_OTABLEI, value);
}
void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
u16 offset, u16 value)
{
struct b43_phy_g *gphy = dev->phy.g;
u16 addr;
addr = table + offset;
if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) ||
(addr - 1 != gphy->ofdmtab_addr)) {
/* The hardware has a different address in memory. Update it. */
b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE;
}
gphy->ofdmtab_addr = addr;
b43_phy_write(dev, B43_PHY_OTABLEI, value);
}
static bool b43_phy_lcn_load_tx_iir_ofdm_filter(struct b43_wldev *dev,
u8 filter_type)
{
int i, j;
u16 phy_regs[] = { 0x90f, 0x900, 0x901, 0x906, 0x907, 0x908, 0x902,
0x903, 0x909, 0x90a, 0x90b, 0x904, 0x905, 0x90c,
0x90d, 0x90e };
struct lcn_tx_iir_filter tx_iir_filters_ofdm[] = {
{ 0, { 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0,
0x0, 0x278, 0xfea0, 0x80, 0x100, 0x80 } },
{ 1, { 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50, 750,
0xFE2B, 212, 0xFFCE, 212 } },
{ 2, { 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748,
0xFEF2, 128, 0xFFE2, 128 } },
};
for (i = 0; i < ARRAY_SIZE(tx_iir_filters_ofdm); i++) {
if (tx_iir_filters_ofdm[i].type == filter_type) {
for (j = 0; j < 16; j++)
b43_phy_write(dev, phy_regs[j],
tx_iir_filters_ofdm[i].values[j]);
return true;
}
}
return false;
}
static u16 lo_measure_feedthrough(struct b43_wldev *dev,
u16 lna, u16 pga, u16 trsw_rx)
{
struct b43_phy *phy = &dev->phy;
u16 rfover;
u16 feedthrough;
if (phy->gmode) {
lna <<= B43_PHY_RFOVERVAL_LNA_SHIFT;
pga <<= B43_PHY_RFOVERVAL_PGA_SHIFT;
B43_WARN_ON(lna & ~B43_PHY_RFOVERVAL_LNA);
B43_WARN_ON(pga & ~B43_PHY_RFOVERVAL_PGA);
/*FIXME This assertion fails B43_WARN_ON(trsw_rx & ~(B43_PHY_RFOVERVAL_TRSWRX |
B43_PHY_RFOVERVAL_BW));
*/
trsw_rx &= (B43_PHY_RFOVERVAL_TRSWRX | B43_PHY_RFOVERVAL_BW);
/* Construct the RF Override Value */
rfover = B43_PHY_RFOVERVAL_UNK;
rfover |= pga;
rfover |= lna;
rfover |= trsw_rx;
if ((dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA)
&& phy->rev > 6)
rfover |= B43_PHY_RFOVERVAL_EXTLNA;
b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
udelay(10);
rfover |= B43_PHY_RFOVERVAL_BW_LBW;
b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
udelay(10);
rfover |= B43_PHY_RFOVERVAL_BW_LPF;
b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
udelay(10);
b43_phy_write(dev, B43_PHY_PGACTL, 0xF300);
} else {
pga |= B43_PHY_PGACTL_UNKNOWN;
b43_phy_write(dev, B43_PHY_PGACTL, pga);
udelay(10);
pga |= B43_PHY_PGACTL_LOWBANDW;
b43_phy_write(dev, B43_PHY_PGACTL, pga);
udelay(10);
pga |= B43_PHY_PGACTL_LPF;
b43_phy_write(dev, B43_PHY_PGACTL, pga);
}
udelay(21);
feedthrough = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
/* This is a good place to check if we need to relax a bit,
* as this is the main function called regularly
* in the LO calibration. */
cond_resched();
return feedthrough;
}
static void b43_wa_analog(struct b43_wldev *dev)
{
struct b43_phy *phy = &dev->phy;
u16 ofdmrev;
ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION;
if (ofdmrev > 2) {
if (phy->type == B43_PHYTYPE_A)
b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
else
b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
} else {
b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
}
}
static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
{//TODO
struct b43_phy *phy = &dev->phy;
u64 hf;
u16 tmp;
int autodiv = 0;
if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
autodiv = 1;
hf = b43_hf_read(dev);
hf &= ~B43_HF_ANTDIVHELP;
b43_hf_write(dev, hf);
tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
tmp &= ~B43_PHY_BBANDCFG_RXANT;
tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
<< B43_PHY_BBANDCFG_RXANT_SHIFT;
b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
if (autodiv) {
tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
if (antenna == B43_ANTENNA_AUTO0)
tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
else
tmp |= B43_PHY_ANTDWELL_AUTODIV1;
b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
}
if (phy->rev < 3) {
tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
tmp = (tmp & 0xFF00) | 0x24;
b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
} else {
tmp = b43_phy_read(dev, B43_PHY_OFDM61);
tmp |= 0x10;
b43_phy_write(dev, B43_PHY_OFDM61, tmp);
if (phy->analog == 3) {
b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
0x1D);
b43_phy_write(dev, B43_PHY_ADIVRELATED,
8);
} else {
b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
0x3A);
tmp =
b43_phy_read(dev,
B43_PHY_ADIVRELATED);
tmp = (tmp & 0xFF00) | 8;
b43_phy_write(dev, B43_PHY_ADIVRELATED,
tmp);
}
}
hf |= B43_HF_ANTDIVHELP;
b43_hf_write(dev, hf);
}
/* wlc_lcnphy_set_tx_gain */
static void b43_phy_lcn_set_tx_gain(struct b43_wldev *dev,
struct lcn_tx_gains *target_gains)
{
u16 pa_gain = b43_phy_lcn_get_pa_gain(dev);
b43_phy_write(dev, 0x4b5,
(target_gains->gm_gain | (target_gains->pga_gain << 8)));
b43_phy_maskset(dev, 0x4fb, ~0x7fff,
(target_gains->pad_gain | (pa_gain << 8)));
b43_phy_write(dev, 0x4fc,
(target_gains->gm_gain | (target_gains->pga_gain << 8)));
b43_phy_maskset(dev, 0x4fd, ~0x7fff,
(target_gains->pad_gain | (pa_gain << 8)));
b43_phy_lcn_set_dac_gain(dev, target_gains->dac_gain);
b43_phy_lcn_set_tx_gain_override(dev, true);
}
static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
{
unsigned int i;
u16 val;
val = 0x1E1F;
for (i = 0; i < 16; i++) {
b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
val -= 0x202;
}
val = 0x3E3F;
for (i = 0; i < 16; i++) {
b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
val -= 0x202;
}
b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
}
static u16 lo_b_r15_loop(struct b43_wldev *dev)
{
int i;
u16 ret = 0;
for (i = 0; i < 10; i++) {
b43_phy_write(dev, 0x0015, 0xAFA0);
udelay(1);
b43_phy_write(dev, 0x0015, 0xEFA0);
udelay(10);
b43_phy_write(dev, 0x0015, 0xFFA0);
udelay(40);
ret += b43_phy_read(dev, 0x002C);
}
return ret;
}
static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
{
struct b43_phy_ht *htphy = dev->phy.ht;
static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
B43_PHY_HT_RF_CTL_INT_C2,
B43_PHY_HT_RF_CTL_INT_C3 };
int i;
if (enable) {
for (i = 0; i < 3; i++)
b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
} else {
for (i = 0; i < 3; i++)
htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
/* TODO: Does 5GHz band use different value (not 0x0400)? */
for (i = 0; i < 3; i++)
b43_phy_write(dev, regs[i], 0x0400);
}
}
/* wlc_phy_init_lcnphy */
static int b43_phy_lcn_op_init(struct b43_wldev *dev)
{
struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;
b43_phy_set(dev, 0x44a, 0x80);
b43_phy_mask(dev, 0x44a, 0x7f);
b43_phy_set(dev, 0x6d1, 0x80);
b43_phy_write(dev, 0x6d0, 0x7);
b43_phy_lcn_afe_set_unset(dev);
b43_phy_write(dev, 0x60a, 0xa0);
b43_phy_write(dev, 0x46a, 0x19);
b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
b43_phy_lcn_tables_init(dev);
b43_phy_lcn_rev0_baseband_init(dev);
b43_phy_lcn_bu_tweaks(dev);
if (dev->phy.radio_ver == 0x2064)
b43_radio_2064_init(dev);
else
B43_WARN_ON(1);
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
b43_phy_lcn_tx_pwr_ctl_init(dev);
b43_switch_channel(dev, dev->phy.channel);
bcma_chipco_regctl_maskset(cc, 0, 0xf, 0x9);
bcma_chipco_chipctl_maskset(cc, 0, 0, 0x03cddddd);
/* TODO */
b43_phy_set(dev, 0x448, 0x4000);
udelay(100);
b43_phy_mask(dev, 0x448, ~0x4000);
/* TODO */
return 0;
}
/* wlc_lcnphy_txrx_spur_avoidance_mode */
static void b43_phy_lcn_txrx_spur_avoidance_mode(struct b43_wldev *dev,
bool enable)
{
if (enable) {
b43_phy_write(dev, 0x942, 0x7);
b43_phy_write(dev, 0x93b, ((1 << 13) + 23));
b43_phy_write(dev, 0x93c, ((1 << 13) + 1989));
b43_phy_write(dev, 0x44a, 0x084);
b43_phy_write(dev, 0x44a, 0x080);
b43_phy_write(dev, 0x6d3, 0x2222);
b43_phy_write(dev, 0x6d3, 0x2220);
} else {
b43_phy_write(dev, 0x942, 0x0);
b43_phy_write(dev, 0x93b, ((0 << 13) + 23));
b43_phy_write(dev, 0x93c, ((0 << 13) + 1989));
}
b43_phy_switch_macfreq(dev, enable);
}
static void b43_phy_ww(struct b43_wldev *dev)
{
u16 b, curr_s, best_s = 0xFFFF;
int i;
b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
b43_radio_set(dev, 0x0009, 0x0080);
b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002);
b43_wa_initgains(dev);
b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
b = b43_phy_read(dev, B43_PHY_PWRDOWN);
b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
b43_radio_set(dev, 0x0004, 0x0004);
for (i = 0x10; i <= 0x20; i++) {
b43_radio_write16(dev, 0x0013, i);
curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
if (!curr_s) {
best_s = 0x0000;
break;
} else if (curr_s >= 0x0080)
curr_s = 0x0100 - curr_s;
if (curr_s < best_s)
best_s = curr_s;
}
b43_phy_write(dev, B43_PHY_PWRDOWN, b);
b43_radio_mask(dev, 0x0004, 0xFFFB);
b43_radio_write16(dev, 0x0013, best_s);
b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
for (i = 0; i < 6; i++)
b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
}
void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
if (dev->phy.ops->phy_maskset) {
assert_mac_suspended(dev);
dev->phy.ops->phy_maskset(dev, offset, mask, set);
} else {
b43_phy_write(dev, offset,
(b43_phy_read(dev, offset) & mask) | set);
}
}
static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
enum rfkill_state state)
{
struct b43_phy *phy = &dev->phy;
if (state == RFKILL_STATE_UNBLOCKED) {
if (phy->radio_on)
return;
b43_radio_write16(dev, 0x0004, 0x00C0);
b43_radio_write16(dev, 0x0005, 0x0008);
b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
b43_radio_init2060(dev);
} else {
b43_radio_write16(dev, 0x0004, 0x00FF);
b43_radio_write16(dev, 0x0005, 0x00FB);
b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
}
}
u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
{
u32 ret;
b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
ret = b43_phy_read(dev, B43_PHY_OTABLEQ);
ret <<= 16;
ret |= b43_phy_read(dev, B43_PHY_OTABLEI);
return ret;
}
void b43_radio_init2060(struct b43_wldev *dev)
{
b43_radio_write16(dev, 0x0004, 0x00C0);
b43_radio_write16(dev, 0x0005, 0x0008);
b43_radio_write16(dev, 0x0009, 0x0040);
b43_radio_write16(dev, 0x0005, 0x00AA);
b43_radio_write16(dev, 0x0032, 0x008F);
b43_radio_write16(dev, 0x0006, 0x008F);
b43_radio_write16(dev, 0x0034, 0x008F);
b43_radio_write16(dev, 0x002C, 0x0007);
b43_radio_write16(dev, 0x0082, 0x0080);
b43_radio_write16(dev, 0x0080, 0x0000);
b43_radio_write16(dev, 0x003F, 0x00DA);
b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
msleep(1); /* delay 400usec */
b43_radio_write16(dev, 0x0081,
(b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
msleep(1); /* delay 400usec */
b43_radio_write16(dev, 0x0005,
(b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
b43_radio_write16(dev, 0x0081,
(b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
b43_radio_write16(dev, 0x0005,
(b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
b43_phy_write(dev, 0x0063, 0xDDC6);
b43_phy_write(dev, 0x0069, 0x07BE);
b43_phy_write(dev, 0x006A, 0x0000);
aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
msleep(1);
}
void b43_lcntab_write(struct b43_wldev *dev, u32 offset, u32 value)
{
u32 type;
type = offset & B43_LCNTAB_TYPEMASK;
offset &= 0xFFFF;
switch (type) {
case B43_LCNTAB_8BIT:
B43_WARN_ON(value & ~0xFF);
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value);
break;
case B43_LCNTAB_16BIT:
B43_WARN_ON(value & ~0xFFFF);
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value);
break;
case B43_LCNTAB_32BIT:
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, value >> 16);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value & 0xFFFF);
break;
default:
B43_WARN_ON(1);
}
return;
}
void b43_lcntab_write_bulk(struct b43_wldev *dev, u32 offset,
unsigned int nr_elements, const void *_data)
{
u32 type, value;
const u8 *data = _data;
unsigned int i;
type = offset & B43_LCNTAB_TYPEMASK;
offset &= ~B43_LCNTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset);
for (i = 0; i < nr_elements; i++) {
switch (type) {
case B43_LCNTAB_8BIT:
value = *data;
data++;
B43_WARN_ON(value & ~0xFF);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value);
break;
case B43_LCNTAB_16BIT:
value = *((u16 *)data);
data += 2;
B43_WARN_ON(value & ~0xFFFF);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value);
break;
case B43_LCNTAB_32BIT:
value = *((u32 *)data);
data += 4;
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI,
value >> 16);
b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO,
value & 0xFFFF);
break;
default:
B43_WARN_ON(1);
}
}
}
static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
u16 wait)
{
struct b43_phy_ht *phy_ht = dev->phy.ht;
u16 save_seq_mode;
int i;
for (i = 0; i < 3; i++) {
if (phy_ht->bb_mult_save[i] < 0)
phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
}
b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
if (loops != 0xFFFF)
loops--;
b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
/* TODO: find out mask bits! Do we need more function arguments? */
b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
for (i = 0; i < 100; i++) {
if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
i = 0;
break;
}
udelay(10);
}
if (i)
b43err(dev->wl, "run samples timeout\n");
b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
}
