//
//===============================================
// adc 自校
//===============================================
void c_adc::calibrate(const adc_dev *dev) {
__io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
__io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
*rstcal_bit = 1;
while (*rstcal_bit);
*cal_bit = 1;
while (*cal_bit);
}
/**
* @brief Calibrate an ADC peripheral
* @param dev adc device
*/
void adc_calibrate(const adc_dev *dev) {
#ifndef STM32F2
__io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
__io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
*rstcal_bit = 1;
while (*rstcal_bit)
;
*cal_bit = 1;
while (*cal_bit)
;
#endif
}
/**
* Initialize the RTC interface, and enable access to its register map and
* the backup registers.
*/
void rtc_init(rtc_clk_src src) {
bkp_init(); // turn on peripheral clocks to PWR and BKP and reset the backup domain via RCC registers.
// (we reset the backup domain here because we must in order to change the rtc clock source).
bkp_enable_writes(); // enable writes to the backup registers and the RTC registers via the DBP bit in the PWR control register
RCC_BASE->BDCR &= ~RCC_BDCR_RTCSEL; // Clear the RTC clock source select field
switch (src) {
case RTCSEL_NONE:
RCC_BASE->BDCR |= RCC_BDCR_RTCSEL_NONE;
break;
case RTCSEL_LSE:
rcc_start_lse();
RCC_BASE->BDCR |= RCC_BDCR_RTCSEL_LSE;
break;
default:
case RTCSEL_LSI:
case RTCSEL_DEFAULT:
rcc_start_lsi();
RCC_BASE->BDCR |= RCC_BDCR_RTCSEL_LSI;
break;
case RTCSEL_HSE: // This selection uses HSE/128 as the RTC source (i.e. 64 kHz with an 8 mHz xtal)
// assume the HSE clock is running (see rcc_clk_init())
RCC_BASE->BDCR |= RCC_BDCR_RTCSEL_HSE;
break;
}
*bb_perip(&RCC_BASE->BDCR, RCC_BDCR_RTCEN_BIT) = 1; // Enable the RTC
rtc_wait_finished();
}
/* A special-case dispatch routine for single-interrupt NVIC lines.
* This function assumes that the interrupt corresponding to `RTC_ALARM_INTERRUPT' has
* in fact occurred (i.e., it doesn't check DIER & SR). */
void __irq_rtcalarm(void) {
void (*handler)(void) = RTC->handlers[RTC_ALARM_SPECIFIC_INTERRUPT];
if (handler) {
handler();
*bb_perip(&EXTI_BASE->PR, EXTI_RTC_ALARM_BIT) = 1;
//asm volatile("nop"); // See comment in exti.c. Doesn't seem to be required.
//asm volatile("nop");
}
}
/**
* @brief Turn on the hardware prefetcher.
*/
void flash_enable_prefetch(void) {
*bb_perip(&FLASH_BASE->ACR, FLASH_ACR_PRFTBE_BIT) = 1;
}
inline void bb_peri_set_bit(volatile void *address, uint32 bit, uint8 val) {
*bb_perip(address, bit) = val;
}
inline uint8 bb_peri_get_bit(volatile void *address, uint32 bit) {
return *bb_perip(address, bit);
}
