//! Initialises BDM module for the given target type //! //! @param target = Target processor (see \ref TargetType_t) //! uint8_t bdm_setTarget(uint8_t target) { uint8_t rc = BDM_RC_OK; #ifdef RESET_IN_PER RESET_IN_PER = 1; // Needed for input level translation to 5V #endif #ifdef RESET_OUT_PER RESET_OUT_PER = 1; // Holds RESET_OUT inactive when unused #endif if (target == T_OFF) { bdm_off(); // Turn off the interface } bdm_interfaceOff(); rc = bdm_clearStatus(); if (rc != BDM_RC_OK) { return rc; } cable_status.target_type = target; // Assume mode is valid switch (target) { #if TARGET_CAPABILITY & CAP_S12Z case T_HCS12Z : #endif #if (TARGET_CAPABILITY & (CAP_HCS12|CAP_S12Z)) case T_HC12: bdm_option.useResetSignal = 1; // Must use RESET signal on HC12 bdmHCS_init(); break; #endif #if (TARGET_CAPABILITY & CAP_RS08) case T_RS08: #endif #if (TARGET_CAPABILITY & CAP_HCS08) case T_HCS08: #endif #if (TARGET_CAPABILITY & CAP_CFV1) case T_CFV1: #endif #if (TARGET_CAPABILITY & (CAP_RS08|CAP_HCS08|CAP_CFV1)) bdmHCS_init(); break; #endif #if (TARGET_CAPABILITY&CAP_CFVx) case T_CFVx: bdm_option.useResetSignal = 1; // Must use RESET signal on CFVx bdmcf_init(); // Initialise the BDM interface // (void)bdmcf_resync(); // Synchronise with the target (ignore error?) break; #endif #if (TARGET_CAPABILITY&CAP_JTAG) case T_JTAG: #endif #if (TARGET_CAPABILITY&CAP_DSC) case T_MC56F80xx: #endif #if (TARGET_CAPABILITY&(CAP_JTAG|CAP_DSC)) bdm_option.useResetSignal = 1; // Must use RESET signal on JTAG etc jtag_init(); // Initialise JTAG break; #endif #if (TARGET_CAPABILITY&CAP_ARM_JTAG) case T_ARM_JTAG: jtag_init(); // Initialise JTAG break; #endif #if (TARGET_CAPABILITY&CAP_ARM_SWD) case T_ARM_SWD: swd_init(); // Initialise JTAG break; #endif case T_OFF: break; default: bdm_off(); // Turn off the interface (void)bdm_clearStatus(); // Safe mode! return BDM_RC_UNKNOWN_TARGET; } return rc; }
/*! \brief Initialise the system. * * Initialisation of the following: * \li Default port values * \li Watchdog (off), * \li Stack, * \li BDM interface, * \li USB interface. * \li Configure Clock for 48MHz operation */ static void init(void) { // Default ports to inputs PTADD = 0x00; PTBDD = 0x00; #if (CPU==JMxx) PTCDD = 0x00; PTDDD = 0x00; PTEDD = 0x00; PTFDD = 0x00; PTGDD = 0x00; #endif // Turn off important things #if ((HW_CAPABILITY & CAP_FLASH) != 0) (void)bdmSetVpp(BDM_TARGET_VPP_OFF); #endif VDD_OFF(); // Default to Ports have PUPs // Note - this doesn't affect outputs PTAPE = 0xFF; PTBPE = 0xFF; #if (CPU==JMxx) PTCPE = 0xFF; PTDPE = 0xFF; PTEPE = 0xFF; PTFPE = 0xFF; PTGPE = 0xFF; #endif EnableInterrupts; #ifndef SOPT1_BKGDPE_MASK #define SOPT1_BKGDPE_MASK (0) #endif SOPT1 = SOPT1_STOPE_MASK|SOPT1_BKGDPE_MASK; // Disable COP, enable STOP instr. & BKGD pin #if (HW_CAPABILITY&CAP_VDDSENSE) SPMSC1_BGBE = 1; // Enable Bandgap Reference #endif LED_INIT(); clearStack(); initUSB(); // Assumes clock already done (void)bdm_init(); (void)bdm_off(); #ifdef VDD_ON_INITIALLY // For compatibility with original board s/w // The board is powered when initially plugged in #if (VDD_ON_INITIALLY == 3) bdm_option.targetVdd = BDM_TARGET_VDD_3V3; #elif (VDD_ON_INITIALLY == 5) bdm_option.targetVdd = BDM_TARGET_VDD_5; #else #error "Illegal VDD_ON_INITIALLY value" #endif (void)bdm_interfaceOff(); (void)bdm_setTargetVdd(); #endif #if (DEBUG&SCI_DEBUG) != 0) debugSCIInit(); #endif }