Ejemplo n.º 1
0
void show_regs(struct pt_regs *fp)
{
#ifdef CONFIG_DEBUG_VERBOSE
	char buf [150];
	struct irqaction *action;
	unsigned int i;
	unsigned long flags = 0;
	unsigned int cpu = smp_processor_id();
	unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();

	verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
	verbose_printk(KERN_NOTICE " SEQSTAT: %08lx  IPEND: %04lx  SYSCFG: %04lx\n",
		(long)fp->seqstat, fp->ipend, fp->syscfg);
	if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
		verbose_printk(KERN_NOTICE "  HWERRCAUSE: 0x%lx\n",
			(fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
#ifdef EBIU_ERRMST
		/* If the error was from the EBIU, print it out */
		if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
			verbose_printk(KERN_NOTICE "  EBIU Error Reason  : 0x%04x\n",
				bfin_read_EBIU_ERRMST());
			verbose_printk(KERN_NOTICE "  EBIU Error Address : 0x%08x\n",
				bfin_read_EBIU_ERRADD());
		}
#endif
	}
Ejemplo n.º 2
0
void show_regs(struct pt_regs *fp)
{
	char buf[150];
	struct irqaction *action;
	unsigned int i;
	unsigned long flags = 0;
	unsigned int cpu = raw_smp_processor_id();
	unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();

	pr_notice("\n");
	if (CPUID != bfin_cpuid())
		pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
			"but running on:0x%04x (Rev %d)\n",
			CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());

	pr_notice("ADSP-%s-0.%d",
		CPU, bfin_compiled_revid());

	if (bfin_compiled_revid() !=  bfin_revid())
		pr_cont("(Detected 0.%d)", bfin_revid());

	pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
		get_cclk()/1000000, get_sclk()/1000000,
#ifdef CONFIG_MPU
		"mpu on"
#else
		"mpu off"
#endif
		);

	if(board_rom_type())
		pr_notice("%s", linux_banner_stockui);
	else
		pr_notice("%s", linux_banner);

	pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
	pr_notice(" SEQSTAT: %08lx  IPEND: %04lx  IMASK: %04lx  SYSCFG: %04lx\n",
		(long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
	if (fp->ipend & EVT_IRPTEN)
		pr_notice("  Global Interrupts Disabled (IPEND[4])\n");
	if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
			EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
		pr_notice("  Peripheral interrupts masked off\n");
	if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
		pr_notice("  Kernel interrupts masked off\n");
	if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
		pr_notice("  HWERRCAUSE: 0x%lx\n",
			(fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
#ifdef EBIU_ERRMST
		
		if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
			pr_notice("  EBIU Error Reason  : 0x%04x\n",
				bfin_read_EBIU_ERRMST());
			pr_notice("  EBIU Error Address : 0x%08x\n",
				bfin_read_EBIU_ERRADD());
		}
#endif
	}
Ejemplo n.º 3
0
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_8xx)
	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	volatile sit8xx_t *timers = &immap->im_sit;

	/* Hopefully more PowerPC  knowledgable people will add code to display
	 * other useful registers
	 */

	printf ("\nSystem Configuration registers\n"

		"\tIMMR\t0x%08X\n", get_immr(0));

	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);

	printf("\tSWT\t0x%08X",    sysconf->sc_swt);
	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);

	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
		sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
		sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
		sysconf->sc_tesr, sysconf->sc_sdcr);

	printf ("Memory Controller Registers\n"

		"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
	printf ("\n"
		"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
		memctl->memc_mamr, memctl->memc_mbmr );
	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
		memctl->memc_mstat, memctl->memc_mptpr );
	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);

	printf ("\nSystem Integration Timers\n"
		"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
		timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	/*
	 * May be some CPM info here?
	 */

#elif defined (CONFIG_405GP)
	printf ("\n405GP registers; MSR=%08x\n",mfmsr());
	printf ("\nUniversal Interrupt Controller Regs\n"
	    "uicsr    uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
	    "\n"
	    "%08x %08x %08x %08x %08x %08x %08x %08x\n",
	mfdcr(uicsr),
	mfdcr(uicer),
	mfdcr(uiccr),
	mfdcr(uicpr),
	mfdcr(uictr),
	mfdcr(uicmsr),
	mfdcr(uicvr),
	mfdcr(uicvcr));

	puts ("\nMemory (SDRAM) Configuration\n"
	    "besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");

	mtdcr(memcfga,mem_besra);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrsa);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrb);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrsb);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_bear);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mcopt1);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_rtr);		printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_pmit);	printf ("%08x ", mfdcr(memcfgd));

	puts ("\n"
	    "mb0cf    mb1cf    mb2cf    mb3cf    sdtr1    ecccf    eccerr\n");
	mtdcr(memcfga,mem_mb0cf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb1cf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb2cf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb3cf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_sdtr1);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_ecccf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_eccerr);	printf ("%08x ", mfdcr(memcfgd));

	printf ("\n\n"
	    "DMA Channels\n"
	    "dmasr    dmasgc   dmaadr\n"
	    "%08x %08x %08x\n"
	    "dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"
	    "%08x %08x %08x %08x %08x\n"
	    "dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"
	    "%08x %08x %08x %08x %08x\n",
	mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));

	printf (
	    "dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"	"%08x %08x %08x %08x %08x\n"
	    "dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"	"%08x %08x %08x %08x %08x\n",
	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );

	puts ("\n"
	    "External Bus\n"
	    "pbear    pbesr0   pbesr1   epcr\n");
	mtdcr(ebccfga,pbear);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr0);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr1);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,epcr);	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
	mtdcr(ebccfga,pb0cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb0ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3ap);	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb4cr    pb4ap    pb5cr    bp5ap    pb6cr    pb6ap    pb7cr    pb7ap\n");
	mtdcr(ebccfga,pb4cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb4ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb5cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb5ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb6cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb6ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb7cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb7ap);	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n\n");

#elif defined(CONFIG_405EP)
	printf ("\n405EP registers; MSR=%08x\n",mfmsr());
	printf ("\nUniversal Interrupt Controller Regs\n"
	    "uicsr    uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
	    "\n"
	    "%08x %08x %08x %08x %08x %08x %08x %08x\n",
	mfdcr(uicsr),
	mfdcr(uicer),
	mfdcr(uiccr),
	mfdcr(uicpr),
	mfdcr(uictr),
	mfdcr(uicmsr),
	mfdcr(uicvr),
	mfdcr(uicvcr));

	puts ("\nMemory (SDRAM) Configuration\n"
	    "mcopt1   rtr      pmit     mb0cf    mb1cf    sdtr1\n");

	mtdcr(memcfga,mem_mcopt1);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_rtr);		printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_pmit);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb0cf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb1cf);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_sdtr1);	printf ("%08x ", mfdcr(memcfgd));

	printf ("\n\n"
	    "DMA Channels\n"
	    "dmasr    dmasgc   dmaadr\n"			"%08x %08x %08x\n"
	    "dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"	"%08x %08x %08x %08x %08x\n"
	    "dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"	"%08x %08x %08x %08x %08x\n",
	mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));

	printf (
	    "dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"	"%08x %08x %08x %08x %08x\n"
	    "dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"	"%08x %08x %08x %08x %08x\n",
	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );

	puts ("\n"
	    "External Bus\n"
	    "pbear    pbesr0   pbesr1   epcr\n");
	mtdcr(ebccfga,pbear);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr0);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr1);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,epcr);	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
	mtdcr(ebccfga,pb0cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb0ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2ap);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3ap);	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb4cr    pb4ap\n");
	mtdcr(ebccfga,pb4cr);	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb4ap);	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n\n");
#elif defined(CONFIG_5xx)

	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl5xx_t	*memctl = &immap->im_memctl;
	volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
	volatile sit5xx_t	*timers = &immap->im_sit;
	volatile car5xx_t	*car = &immap->im_clkrst;
	volatile uimb5xx_t	*uimb = &immap->im_uimb;

	puts ("\nSystem Configuration registers\n");
	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);

	puts ("\nMemory Controller Registers\n");
	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);

	puts ("\nSystem Integration Timers\n");
	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	puts ("\nClocks and Reset\n");
	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);

	puts ("\nU-Bus to IMB3 Bus Interface\n");
	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
	puts ("\n\n");

#elif defined(CONFIG_MPC5200)
	puts ("\nMPC5200 registers\n");
	printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
	puts ("Memory map registers\n");
	printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS0_START,
		*(volatile ulong*)MPC5XXX_CS0_STOP,
		*(volatile ulong*)MPC5XXX_CS0_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
	printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS1_START,
		*(volatile ulong*)MPC5XXX_CS1_STOP,
		*(volatile ulong*)MPC5XXX_CS1_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
	printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS2_START,
		*(volatile ulong*)MPC5XXX_CS2_STOP,
		*(volatile ulong*)MPC5XXX_CS2_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
	printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS3_START,
		*(volatile ulong*)MPC5XXX_CS3_STOP,
		*(volatile ulong*)MPC5XXX_CS3_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
	printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS4_START,
		*(volatile ulong*)MPC5XXX_CS4_STOP,
		*(volatile ulong*)MPC5XXX_CS4_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
	printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS5_START,
		*(volatile ulong*)MPC5XXX_CS5_STOP,
		*(volatile ulong*)MPC5XXX_CS5_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
	printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS6_START,
		*(volatile ulong*)MPC5XXX_CS6_STOP,
		*(volatile ulong*)MPC5XXX_CS6_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
	printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS7_START,
		*(volatile ulong*)MPC5XXX_CS7_STOP,
		*(volatile ulong*)MPC5XXX_CS7_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
	printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_BOOTCS_START,
		*(volatile ulong*)MPC5XXX_BOOTCS_STOP,
		*(volatile ulong*)MPC5XXX_BOOTCS_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
	printf ("\tSDRAMCS0: %08lX\n",
		*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
	printf ("\tSDRAMCS1: %08lX\n",
		*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_MPC86xx)
	mpc86xx_reginfo();

#elif defined(CONFIG_BLACKFIN)
	puts("\nSystem Configuration registers\n");

	puts("\nPLL Registers\n");
	printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
		bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
	printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
		bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
	printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());

	puts("\nEBIU AMC Registers\n");
	printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
	printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
		bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
# ifdef EBIU_MODE
	printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
		bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
	printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
		bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
# endif

# ifdef EBIU_RSTCTL
	puts("\nEBIU DDR Registers\n");
	printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
		bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
	printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
		bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
	printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
		bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
	printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
		bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
# else
	puts("\nEBIU SDC Registers\n");
	printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
		bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
	printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
		bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif

#endif /* CONFIG_BLACKFIN */

	return 0;
}
Ejemplo n.º 4
0
static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
                      char * const argv[])
{
#if defined(CONFIG_8xx)
    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;
    volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
    volatile sit8xx_t *timers = &immap->im_sit;

    /* Hopefully more PowerPC  knowledgable people will add code to display
     * other useful registers
     */

    printf ("\nSystem Configuration registers\n"

            "\tIMMR\t0x%08X\n", get_immr(0));

    printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
    printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);

    printf("\tSWT\t0x%08X",    sysconf->sc_swt);
    printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);

    printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
           sysconf->sc_sipend, sysconf->sc_simask);
    printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
           sysconf->sc_siel, sysconf->sc_sivec);
    printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
           sysconf->sc_tesr, sysconf->sc_sdcr);

    printf ("Memory Controller Registers\n"

            "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
    printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
    printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
    printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
    printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
    printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
    printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
    printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
    printf ("\n"
            "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
            memctl->memc_mamr, memctl->memc_mbmr );
    printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
           memctl->memc_mstat, memctl->memc_mptpr );
    printf("\tmdr\t0x%08X \n", memctl->memc_mdr);

    printf ("\nSystem Integration Timers\n"
            "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
            timers->sit_tbscr, timers->sit_rtcsc);
    printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

    /*
     * May be some CPM info here?
     */

#elif defined (CONFIG_4xx)
    ppc4xx_reginfo();
#elif defined(CONFIG_5xx)

    volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
    volatile memctl5xx_t	*memctl = &immap->im_memctl;
    volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
    volatile sit5xx_t	*timers = &immap->im_sit;
    volatile car5xx_t	*car = &immap->im_clkrst;
    volatile uimb5xx_t	*uimb = &immap->im_uimb;

    puts ("\nSystem Configuration registers\n");
    printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
    printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
    printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
    printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
    printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);

    puts ("\nMemory Controller Registers\n");
    printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
    printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
    printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
    printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
    printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
    printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);

    puts ("\nSystem Integration Timers\n");
    printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
    printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

    puts ("\nClocks and Reset\n");
    printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);

    puts ("\nU-Bus to IMB3 Bus Interface\n");
    printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
    puts ("\n\n");

#elif defined(CONFIG_MPC5200)
    puts ("\nMPC5200 registers\n");
    printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
    puts ("Memory map registers\n");
    printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS0_START,
            *(volatile ulong*)MPC5XXX_CS0_STOP,
            *(volatile ulong*)MPC5XXX_CS0_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
    printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS1_START,
            *(volatile ulong*)MPC5XXX_CS1_STOP,
            *(volatile ulong*)MPC5XXX_CS1_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
    printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS2_START,
            *(volatile ulong*)MPC5XXX_CS2_STOP,
            *(volatile ulong*)MPC5XXX_CS2_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
    printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS3_START,
            *(volatile ulong*)MPC5XXX_CS3_STOP,
            *(volatile ulong*)MPC5XXX_CS3_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
    printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS4_START,
            *(volatile ulong*)MPC5XXX_CS4_STOP,
            *(volatile ulong*)MPC5XXX_CS4_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
    printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS5_START,
            *(volatile ulong*)MPC5XXX_CS5_STOP,
            *(volatile ulong*)MPC5XXX_CS5_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
    printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS6_START,
            *(volatile ulong*)MPC5XXX_CS6_STOP,
            *(volatile ulong*)MPC5XXX_CS6_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
    printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_CS7_START,
            *(volatile ulong*)MPC5XXX_CS7_STOP,
            *(volatile ulong*)MPC5XXX_CS7_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
    printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
            *(volatile ulong*)MPC5XXX_BOOTCS_START,
            *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
            *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
            (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
    printf ("\tSDRAMCS0: %08lX\n",
            *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
    printf ("\tSDRAMCS1: %08lX\n",
            *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_MPC86xx)
    mpc86xx_reginfo();

#elif defined(CONFIG_MPC85xx)
    mpc85xx_reginfo();

#elif defined(CONFIG_BLACKFIN)
    puts("\nSystem Configuration registers\n");
#ifndef __ADSPBF60x__
    puts("\nPLL Registers\n");
    printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
           bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
    printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
           bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
    printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());

    puts("\nEBIU AMC Registers\n");
    printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
    printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
           bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
# ifdef EBIU_MODE
    printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
           bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
    printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
           bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
# endif

# ifdef EBIU_RSTCTL
    puts("\nEBIU DDR Registers\n");
    printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
           bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
    printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
           bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
    printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
           bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
    printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
           bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
# else
    puts("\nEBIU SDC Registers\n");
    printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
           bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
    printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
           bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif
#else
    puts("\nCGU Registers\n");
    printf("\tCGU_DIV:   0x%08x   CGU_CTL:      0x%08x\n",
           bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
    printf("\tCGU_STAT:  0x%08x   CGU_LOCKCNT:  0x%08x\n",
           bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());

    puts("\nSMC DDR Registers\n");
    printf("\tDDR_CFG:   0x%08x   DDR_TR0:      0x%08x\n",
           bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
    printf("\tDDR_TR1:   0x%08x   DDR_TR2:      0x%08x\n",
           bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
    printf("\tDDR_MR:    0x%08x   DDR_EMR1:     0x%08x\n",
           bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
    printf("\tDDR_CTL:   0x%08x   DDR_STAT:     0x%08x\n",
           bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
    printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
#endif
#endif /* CONFIG_BLACKFIN */

    return 0;
}