void uart1_puts(const char *str, int size)
{
if(size>SEND_RING_SIZE)
panicf("Too much data passed to uart1_puts");
/* Wait for the previous transfer to finish */
while(uart1_send_count>0);
memcpy(uart1_send_buffer_ring, str, size);
/* Disable interrupt while modifying the pointers */
bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
uart1_send_count=size;
uart1_send_read=0;
/* prime the hardware buffer */
while(((IO_UART1_TFCR & 0x3f) < 0x20) && (uart1_send_count > 0))
{
IO_UART1_DTRR=uart1_send_buffer_ring[uart1_send_read++];
uart1_send_count--;
}
/* Enable interrupt */
bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
}
bool timer_start(void)
{
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
stop_timer();
/* enable TIMER0 clock */
bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR0);
/* Turn Timer0 to Free Run mode */
IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_FREE_RUN;
/* enable TIMER0 interrupt */
bitset16(&IO_INTC_EINT0, INTR_EINT0_TMR0);
restore_interrupt(oldstatus);
return true;
}
void lcd_awake(void)
{
if (!lcd_on)
{
lcd_on = true;
/* enable video encoder clock */
bitset16(&IO_CLK_MOD1, CLK_MOD1_VENC);
/* enable video encoder */
bitset16(&IO_VID_ENC_VMOD, 0x01);
avr_hid_lcm_wake();
send_event(LCD_EVENT_ACTIVATION, NULL);
lcd_update();
}
}
void pcm_play_dma_init(void)
{
IO_INTC_IRQ0 = INTR_IRQ0_IMGBUF;
bitset16(&IO_INTC_EINT0, INTR_EINT0_IMGBUF);
/* Set this as a FIQ */
bitset16(&IO_INTC_FISEL0, INTR_EINT0_IMGBUF);
/* Enable the HPIB clock */
bitset16(&IO_CLK_MOD0, (CLK_MOD0_HPIB | CLK_MOD0_DSP));
IO_SDRAM_SDDMASEL = 0x24;
IO_DSPC_HPIB_CONTROL = 1 << 10 | 1 << 9 | 1 << 8 | 1 << 7 | 1 << 3 | 1 << 0;
dsp_reset();
dsp_load(dsp_image);
DSP_(_dma0_stopped)=1;
dsp_wake();
}
void uart1_clear_queue(void)
{
/* Disable interrupt while modifying the pointers */
bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
uart1_receive_write=0;
uart1_receive_count=0;
uart1_receive_read=0;
/* Enable interrupt */
bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
}
void uart_init(void)
{
/* Enable UART clock */
bitset16(&IO_CLK_MOD2, CLK_MOD2_UART1);
// 8-N-1
IO_UART1_MSR = 0xC400;
IO_UART1_BRSR = 0x0057;
IO_UART1_RFCR = 0x8020; /* Trigger later */
IO_UART1_TFCR = 0x0000; /* Trigger level */
/* init the receive buffer */
uart1_receive_count=0;
uart1_receive_read=0;
uart1_receive_write=0;
/* init the send buffer */
uart1_send_count=0;
uart1_send_read=0;
uart1_send_write=0;
/* Enable the interrupt */
bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
}
/* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/
int uart1_gets_queue(char *str, int size)
{
/* Disable the interrupt while modifying the pointers */
bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
int retval;
if(uart1_receive_count<size)
{
retval= -1;
}
else
{
if(uart1_receive_read+size<=RECEIVE_RING_SIZE)
{
memcpy(str,uart1_receive_buffer_ring+uart1_receive_read,size);
uart1_receive_read+=size;
}
else
{
int tempcount=(RECEIVE_RING_SIZE-uart1_receive_read);
memcpy(str,uart1_receive_buffer_ring+uart1_receive_read,tempcount);
memcpy(str+tempcount,uart1_receive_buffer_ring,size-tempcount);
uart1_receive_read=size-tempcount;
}
uart1_receive_count-=size;
retval=uart1_receive_count;
}
/* Enable the interrupt */
bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
return retval;
}
bool timer_set(long cycles, bool start)
{
int oldlevel;
unsigned int divider=cycles, prescaler=0;
if(cycles<1)
return false;
oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL);
bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR0); /* enable TIMER0 clock */
IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
if (start && pfn_unregister != NULL)
{
pfn_unregister();
pfn_unregister = NULL;
}
oldlevel = disable_irq_save();
/* Increase prescale values starting from 0 to make the cycle count fit */
while(divider>65535 && prescaler<1024)
{
prescaler++;
divider=cycles/(prescaler+1);
}
IO_TIMER0_TMPRSCL = prescaler;
IO_TIMER0_TMDIV = divider;
restore_irq(oldlevel);
return true;
}
void lcd_init_device(void)
{
unsigned int addr;
/* Disable Video Encoder clock */
bitclr16(&IO_CLK_MOD1, CLK_MOD1_VENC);
/* configure GIO39, GIO34 as outputs */
IO_GIO_DIR2 &= ~((1 << 7) /* GIO39 */ | (1 << 2) /* GIO34 */);
IO_GIO_FSEL3 = (IO_GIO_FSEL3 & ~(0x300F)) |
(0x1000) /* GIO39 - FIELD_VENC */ |
(0x4); /* GIO34 - PWM1 (brightness control) */
/* OSD Clock = VENC Clock /2,
CCD clock PCLK,
VENC Clock from PLLA */
IO_CLK_SEL1 = 0x3;
/* Set VENC Clock Division to 11
OF bootloader sets division to 8, vmlinux sets it to 11 */
IO_CLK_DIV3 = (IO_CLK_DIV3 & ~(0x1F00)) | 0xB00;
/* Enable OSD clock */
bitset16(&IO_CLK_MOD1, CLK_MOD1_OSD);
/* magic values based on OF bootloader initialization */
/* Set DAC to powerdown mode (bit 2 to 1 in VMOD) */
IO_VID_ENC_VMOD = 0x2014; /* OF sets 0x2010 */
IO_VID_ENC_VDPRO = 0x80;
IO_VID_ENC_HSPLS = 0x4;
IO_VID_ENC_HINT = 0x4B0;
IO_VID_ENC_HSTART = 0x88;
IO_VID_ENC_HVALID = 0x3C0;
IO_VID_ENC_HSDLY = 0;
IO_VID_ENC_VSPLS = 0x2;
IO_VID_ENC_VINT = 0x152;
IO_VID_ENC_VSTART = 0x6;
IO_VID_ENC_VVALID = 0x140;
IO_VID_ENC_VSDLY = 0;
IO_VID_ENC_DCLKCTL = 0x3;
IO_VID_ENC_DCLKPTN0 = 0xC;
IO_VID_ENC_VDCTL = 0x6000;
IO_VID_ENC_SYNCTL = 0x2;
IO_VID_ENC_LCDOUT = 0x101;
IO_VID_ENC_VMOD = 0x2015; /* OF sets 0x2011 */
/* Copy Rockbox frame buffer to the second framebuffer */
lcd_update();
avr_hid_sync();
avr_hid_lcm_power_on();
/* set framebuffer address - OF sets RAM start address to 0x1000000 */
addr = ((int)FRAME-CONFIG_SDRAM_START)/32;
IO_OSD_OSDWINADH = addr >> 16;
IO_OSD_OSDWIN0ADL = addr & 0xFFFF;
IO_OSD_BASEPX = 0x44;
IO_OSD_BASEPY = 0x6;
IO_OSD_OSDWIN0XP = 0;
IO_OSD_OSDWIN0YP = 0;
IO_OSD_OSDWIN0XL = LCD_WIDTH*2; /* OF bootloader sets 480 */
IO_OSD_OSDWIN0YL = LCD_HEIGHT; /* OF bootloader sets 320 */
IO_OSD_OSDWIN0OFST = 0xF;
IO_OSD_OSDWINMD0 = 0x25FB;/* OF bootloader sets 25C3,
vmlinux changes this to 0x25FB */
IO_OSD_VIDWINMD = 0; /* disable video windows (OF sets 0x03) */
IO_OSD_OSDWINMD1 = 0; /* disable OSD window 1 */
/* Enable Video Encoder and OSD clocks */
bitset16(&IO_CLK_MOD1, CLK_MOD1_VENC | CLK_MOD1_OSD);
/* Enable Video Encoder - RGB666, custom timing */
IO_VID_ENC_VMOD = 0x2015;
avr_hid_lcm_wake();
lcd_on = true;
}
static void dma_lcd_copy_buffer_rect(int x, int y, int width, int height)
{
char *dst, *src;
/* Image buffer A is 4KW, every pixel is one Word */
/* lines is maximum number of lines we can transfer in single run */
int lines = 4096/width;
if (lines > height)
lines = height;
/* Set source and destination addresses */
dst = (char*)(FRAME + LCD_WIDTH*y + x);
src = (char*)(FBADDR(x,y));
/* Flush cache to memory */
commit_dcache();
/* Addresses are relative to start of SDRAM */
src -= CONFIG_SDRAM_START;
dst -= CONFIG_SDRAM_START;
/* Enable Image Buffer clock */
bitset16(&IO_CLK_MOD1, CLK_MOD1_IMGBUF);
/* Use Image Buffer A for DMA */
COP_BUF_MUX0 = (COP_BUF_MUX0 & 0xFFF0) | 0x0003;
/* Setup buffer offsets and transfer width/height */
COP_BUF_LOFST = width;
COP_DMA_XNUM = width;
COP_DMA_YNUM = lines;
/* DMA: No byte SWAP, no transformation, data bus shift down 0 bit */
COP_IMG_MODE &= 0xC0;
/* Set the start address of buffer */
COP_BUF_ADDR = 0x0000;
/* Setup SDRAM stride */
COP_SDEM_LOFST = LCD_WIDTH;
do {
int addr;
addr = (int)src;
addr >>= 1; /* Addresses are in 16-bit words */
/* Setup the registers to initiate the read from SDRAM */
COP_SDEM_ADDRH = addr >> 16;
COP_SDEM_ADDRL = addr & 0xFFFF;
/* Set direction and start */
COP_DMA_CTRL = 0x0001;
COP_DMA_CTRL |= 0x0002;
/* Wait for read to finish */
while (COP_DMA_CTRL & 0x02) {};
addr = (int)dst;
addr >>= 1;
COP_SDEM_ADDRH = addr >> 16;
COP_SDEM_ADDRL = addr & 0xFFFF;
/* Set direction and start transfer */
COP_DMA_CTRL = 0x0000;
COP_DMA_CTRL |= 0x0002;
/* Wait for the transfer to complete */
while (COP_DMA_CTRL & 0x02) {};
/* Decrease height, update pointers */
src += (LCD_WIDTH << 1)*lines;
dst += (LCD_WIDTH << 1)*lines;
height -= lines;
if (height < lines)
{
lines = height;
COP_DMA_YNUM = height;
}
} while (height > 0);
/* Disable Image Buffer clock */
bitclr16(&IO_CLK_MOD1, CLK_MOD1_IMGBUF);
}
