int get_hw_ocv(void)
{
#if defined(CONFIG_POWER_EXT)
return 4001;
#else
kal_int32 adc_result_reg=0;
kal_int32 adc_result=0;
kal_int32 r_val_temp=4;
#if defined(SWCHR_POWER_PATH)
adc_result_reg = pmic_get_register_value(PMIC_RG_ADC_OUT_WAKEUP_SWCHR);
adc_result = (adc_result_reg*r_val_temp*VOLTAGE_FULL_RANGE)/ADC_PRECISE;
bm_print(BM_LOG_CRTI, "[oam] get_hw_ocv (swchr) : adc_result_reg=%d, adc_result=%d\n",
adc_result_reg, adc_result);
#else
adc_result_reg = pmic_get_register_value(PMIC_RG_ADC_OUT_WAKEUP_PCHR);
adc_result = (adc_result_reg*r_val_temp*VOLTAGE_FULL_RANGE)/ADC_PRECISE;
bm_print(BM_LOG_CRTI, "[oam] get_hw_ocv (pchr) : adc_result_reg=%d, adc_result=%d\n",
adc_result_reg, adc_result);
#endif
adc_result += g_hw_ocv_tune_value;
return adc_result;
#endif
}
int get_hw_ocv(void)
{
#if defined(CONFIG_POWER_EXT)
return 4001;
#else
kal_int32 adc_result_reg=0;
kal_int32 adc_result=0;
kal_int32 r_val_temp=4;
#if defined(SWCHR_POWER_PATH)
adc_result_reg = upmu_get_rg_adc_out_wakeup_swchr();
adc_result = (adc_result_reg*r_val_temp*VOLTAGE_FULL_RANGE)/ADC_PRECISE;
bm_print(BM_LOG_CRTI, "[oam] get_hw_ocv (swchr) : adc_result_reg=%d, adc_result=%d\n",
adc_result_reg, adc_result);
#else
adc_result_reg = upmu_get_rg_adc_out_wakeup_pchr();
adc_result = (adc_result_reg*r_val_temp*VOLTAGE_FULL_RANGE)/ADC_PRECISE;
bm_print(BM_LOG_CRTI, "[oam] get_hw_ocv (pchr) : adc_result_reg=%d, adc_result=%d\n",
adc_result_reg, adc_result);
#endif
adc_result += g_hw_ocv_tune_value;
return adc_result;
#endif
}
void sg_print(const Segment* const sg)
{
tl_assert(sg);
VG_(printf)("vc: ");
vc_print(&sg->vc);
VG_(printf)("\n");
bm_print(sg->bm);
}
void fg_bat_l_int_handler(void)
{
bm_print(BM_LOG_CRTI, "[fg_bat_l_int_handler] \n");
pmic_set_register_value(PMIC_RG_LBAT_IRQ_EN_MIN,0);
pmic_set_register_value(PMIC_RG_LBAT_EN_MIN,0);
pmic_set_register_value(PMIC_RG_INT_EN_BAT_L,0);
is_lbat_int=KAL_TRUE;
}
static kal_int32 read_adc_v_bat_temp(void *data)
{
#if defined(CONFIG_POWER_EXT)
*(kal_int32*)(data) = 0;
#else
#if defined(MTK_PCB_TBAT_FEATURE)
int ret = 0, data[4], i, ret_value = 0, ret_temp = 0;
int Channel=1;
if( IMM_IsAdcInitReady() == 0 )
{
bm_print(BM_LOG_CRTI, "[get_tbat_volt] AUXADC is not ready");
return 0;
}
i = times;
while (i--)
{
ret_value = IMM_GetOneChannelValue(Channel, data, &ret_temp);
ret += ret_temp;
bm_print(BM_LOG_FULL, "[get_tbat_volt] ret_temp=%d\n",ret_temp);
}
ret = ret*1500/4096 ;
ret = ret/times;
bm_print(BM_LOG_CRTI, "[get_tbat_volt] Battery output mV = %d\n",ret);
*(kal_int32*)(data) = ret;
#else
bm_print(BM_LOG_FULL, "[read_adc_v_charger] return PMIC_IMM_GetOneChannelValue(4,times,1);\n");
*(kal_int32*)(data) = PMIC_IMM_GetOneChannelValue(VBATTEMP_CHANNEL_NUMBER,*(kal_int32*)(data),1);
#endif
#endif
return STATUS_OK;
}
kal_int32 use_chip_trim_value(kal_int32 not_trim_val)
{
#if defined(CONFIG_POWER_EXT)
return not_trim_val;
#else
kal_int32 ret_val=0;
ret_val=((not_trim_val*chip_diff_trim_value)/1000);
bm_print(BM_LOG_FULL, "[use_chip_trim_value] %d -> %d\n", not_trim_val, ret_val);
return ret_val;
#endif
}
void trigger_hw_ocv(void)
{
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SEL,0x1);
//udelay(50);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SW,0x0);
//udelay(50);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SW,0x1);
while(pmic_get_register_value(PMIC_RG_ADC_RDY_WAKEUP_PCHR)==0)
{
bm_print(BM_LOG_FULL, "[trigger_hw_ocv] delay\n");
udelay(100);
}
}
static kal_int32 fgauge_set_low_battery_interrupt(void *data)
{
#if defined(CONFIG_MTK_HAFG_20)
kal_uint32 voltage=*(kal_uint32*)(data);
kal_uint32 rawdata;
static int eint_init=0;
if(eint_init==0)
{
pmic_register_interrupt_callback(2,fg_bat_l_int_handler);
eint_init=1;
}
is_lbat_int=KAL_FALSE;
pmic_turn_on_clock(KAL_TRUE);
rawdata=voltage*4096/1800/4;
bm_print(BM_LOG_CRTI, "[fgauge_set_low_battery_interrupt] Battery voltage %d %d\n",rawdata,voltage);
// 0:set interrupt
pmic_set_register_value(PMIC_RG_INT_EN_BAT_L,1);
// 1.setup min voltage threshold 3.4v
pmic_set_register_value(PMIC_RG_LBAT_VOLT_MIN,rawdata);
// 2.setup detection period
pmic_set_register_value(PMIC_RG_LBAT_DET_PRD_19_16,0x0);
pmic_set_register_value(PMIC_RG_LBAT_DET_PRD_15_0,0x12f);
// 3.setup max/min debounce time
pmic_set_register_value(PMIC_RG_LBAT_DEBT_MIN,0x5a);//15mins
// 4.turn on IRQ
pmic_set_register_value(PMIC_RG_LBAT_IRQ_EN_MIN,0x1);
// 5. turn on LowBattery Detection
pmic_set_register_value(PMIC_RG_LBAT_EN_MIN,1);
#endif
return STATUS_OK;
}
kal_int32 bm_ctrl_cmd(BATTERY_METER_CTRL_CMD cmd, void *data)
{
kal_int32 status;
if(cmd < BATTERY_METER_CMD_NUMBER)
{
if(bm_func[cmd]==NULL)
{
bm_print(BM_LOG_FULL, "[bm_ctrl_cmd] NULL cmd=%d\n",cmd);
}
else
{
status = bm_func[cmd](data);
}
}
else
return STATUS_UNSUPPORTED;
return status;
}
static kal_int32 get_refresh_hw_ocv(void *data)
{
#if defined(CONFIG_MTK_HAFG_20)
kal_int32 hwocv1,hwocv2;
pmic_turn_on_clock(1);
udelay(30);
hwocv1=get_hw_ocv();
trigger_hw_ocv();
hwocv2=get_hw_ocv();
bm_print(BM_LOG_CRTI, "[bat_get_zcv]%d %d\n",hwocv1,hwocv2);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SEL,0x0);
pmic_turn_on_clock(0);
*(kal_int32*)(data)=hwocv2;
#else
*(kal_int32*)(data)=0;
#endif
return STATUS_OK;
}
//============================================================ //
void get_hw_chip_diff_trim_value(void)
{
#if defined(CONFIG_POWER_EXT)
#else
kal_int32 reg_val_1 = 0;
kal_int32 reg_val_2 = 0;
#if 1
reg_val_1 = upmu_get_reg_value(0x01C4);
reg_val_1 = (reg_val_1 & 0xE000) >> 13;
reg_val_2 = upmu_get_reg_value(0x01C6);
reg_val_2 = (reg_val_2 & 0x0003);
chip_diff_trim_value_4_0 = reg_val_1 | (reg_val_2 << 3);
bm_print(BM_LOG_FULL, "[Chip_Trim] Reg[0x%x]=0x%x, Reg[0x%x]=0x%x, chip_diff_trim_value_4_0=%d\n",
0x01C4, upmu_get_reg_value(0x01C4), 0x01C6, upmu_get_reg_value(0x01C6), chip_diff_trim_value_4_0);
#else
bm_print(BM_LOG_FULL,, "[Chip_Trim] need check reg number\n");
#endif
switch(chip_diff_trim_value_4_0) {
case 0:
chip_diff_trim_value = 1000;
bm_print(BM_LOG_FULL, "[Chip_Trim] chip_diff_trim_value = 1000\n");
break;
case 1:
chip_diff_trim_value = 1005;
break;
case 2:
chip_diff_trim_value = 1010;
break;
case 3:
chip_diff_trim_value = 1015;
break;
case 4:
chip_diff_trim_value = 1020;
break;
case 5:
chip_diff_trim_value = 1025;
break;
case 6:
chip_diff_trim_value = 1030;
break;
case 7:
chip_diff_trim_value = 1035;
break;
case 8:
chip_diff_trim_value = 1040;
break;
case 9:
chip_diff_trim_value = 1045;
break;
case 10:
chip_diff_trim_value = 1050;
break;
case 11:
chip_diff_trim_value = 1055;
break;
case 12:
chip_diff_trim_value = 1060;
break;
case 13:
chip_diff_trim_value = 1065;
break;
case 14:
chip_diff_trim_value = 1070;
break;
case 15:
chip_diff_trim_value = 1075;
break;
case 31:
chip_diff_trim_value = 995;
break;
case 30:
chip_diff_trim_value = 990;
break;
case 29:
chip_diff_trim_value = 985;
break;
case 28:
chip_diff_trim_value = 980;
break;
case 27:
chip_diff_trim_value = 975;
break;
case 26:
chip_diff_trim_value = 970;
break;
case 25:
chip_diff_trim_value = 965;
break;
case 24:
chip_diff_trim_value = 960;
break;
case 23:
chip_diff_trim_value = 955;
break;
case 22:
chip_diff_trim_value = 950;
break;
case 21:
chip_diff_trim_value = 945;
break;
case 20:
chip_diff_trim_value = 940;
break;
case 19:
chip_diff_trim_value = 935;
break;
case 18:
chip_diff_trim_value = 930;
break;
case 17:
chip_diff_trim_value = 925;
break;
default:
bm_print(BM_LOG_FULL, "[Chip_Trim] Invalid value(%d)\n", chip_diff_trim_value_4_0);
break;
}
bm_print(BM_LOG_FULL, "[Chip_Trim] %d,%d\n",
chip_diff_trim_value_4_0, chip_diff_trim_value);
#endif
}
/** Compute a bitmap that represents the union of all memory accesses of all
* segments that are unordered to the current segment of the thread tid.
*/
static void thread_compute_danger_set(struct bitmap** danger_set,
const DrdThreadId tid)
{
Segment* p;
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
&& tid != DRD_INVALID_THREADID);
tl_assert(tid == s_drd_running_tid);
s_update_danger_set_count++;
s_danger_set_bitmap_creation_count -= bm_get_bitmap_creation_count();
s_danger_set_bitmap2_creation_count -= bm_get_bitmap2_creation_count();
if (*danger_set)
{
bm_delete(*danger_set);
}
*danger_set = bm_new();
if (s_trace_danger_set)
{
char msg[256];
VG_(snprintf)(msg, sizeof(msg),
"computing danger set for thread %d/%d with vc ",
DrdThreadIdToVgThreadId(tid), tid);
vc_snprint(msg + VG_(strlen)(msg),
sizeof(msg) - VG_(strlen)(msg),
&s_threadinfo[tid].last->vc);
VG_(message)(Vg_UserMsg, "%s", msg);
}
p = s_threadinfo[tid].last;
{
unsigned j;
if (s_trace_danger_set)
{
char msg[256];
VG_(snprintf)(msg, sizeof(msg),
"danger set: thread [%d] at vc ",
tid);
vc_snprint(msg + VG_(strlen)(msg),
sizeof(msg) - VG_(strlen)(msg),
&p->vc);
VG_(message)(Vg_UserMsg, "%s", msg);
}
for (j = 0; j < sizeof(s_threadinfo) / sizeof(s_threadinfo[0]); j++)
{
if (j != tid && IsValidDrdThreadId(j))
{
const Segment* q;
for (q = s_threadinfo[j].last; q; q = q->prev)
{
if (! vc_lte(&q->vc, &p->vc) && ! vc_lte(&p->vc, &q->vc))
{
if (s_trace_danger_set)
{
char msg[256];
VG_(snprintf)(msg, sizeof(msg),
"danger set: [%d] merging segment ", j);
vc_snprint(msg + VG_(strlen)(msg),
sizeof(msg) - VG_(strlen)(msg),
&q->vc);
VG_(message)(Vg_UserMsg, "%s", msg);
}
bm_merge2(*danger_set, q->bm);
}
else
{
if (s_trace_danger_set)
{
char msg[256];
VG_(snprintf)(msg, sizeof(msg),
"danger set: [%d] ignoring segment ", j);
vc_snprint(msg + VG_(strlen)(msg),
sizeof(msg) - VG_(strlen)(msg),
&q->vc);
VG_(message)(Vg_UserMsg, "%s", msg);
}
}
}
}
}
}
s_danger_set_bitmap_creation_count += bm_get_bitmap_creation_count();
s_danger_set_bitmap2_creation_count += bm_get_bitmap2_creation_count();
if (0 && s_trace_danger_set)
{
VG_(message)(Vg_UserMsg, "[%d] new danger set:", tid);
bm_print(*danger_set);
VG_(message)(Vg_UserMsg, "[%d] end of new danger set.", tid);
}
}
