void C1_MacroAssembler::unlock_object(Register Rmark, Register Roop, Register Rbox, Label& slow_case) {
assert_different_registers(Rmark, Roop, Rbox);
Label done;
Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
assert(mark_addr.disp() == 0, "cas must take a zero displacement");
if (UseBiasedLocking) {
// load the object out of the BasicObjectLock
ld_ptr(Rbox, BasicObjectLock::obj_offset_in_bytes(), Roop);
verify_oop(Roop);
biased_locking_exit(mark_addr, Rmark, done);
}
// Test first it it is a fast recursive unlock
ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
br_null_short(Rmark, Assembler::pt, done);
if (!UseBiasedLocking) {
// load object
ld_ptr(Rbox, BasicObjectLock::obj_offset_in_bytes(), Roop);
verify_oop(Roop);
}
// Check if it is still a light weight lock, this is is true if we see
// the stack address of the basicLock in the markOop of the object
cas_ptr(mark_addr.base(), Rbox, Rmark);
cmp(Rbox, Rmark);
brx(Assembler::notEqual, false, Assembler::pn, slow_case);
delayed()->nop();
// Done
bind(done);
}
OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
// make a frame and preserve the caller's caller-save registers
OopMap* oop_map = save_live_registers(sasm);
// call the runtime patching routine, returns non-zero if nmethod got deopted.
int call_offset = __ call_RT(noreg, noreg, target);
OopMapSet* oop_maps = new OopMapSet();
oop_maps->add_gc_map(call_offset, oop_map);
// re-execute the patched instruction or, if the nmethod was deoptmized, return to the
// deoptimization handler entry that will cause re-execution of the current bytecode
DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
assert(deopt_blob != NULL, "deoptimization blob must have been created");
Label no_deopt;
__ br_null_short(O0, Assembler::pt, no_deopt);
// return to the deoptimization handler entry for unpacking and rexecute
// if we simply returned the we'd deopt as if any call we patched had just
// returned.
restore_live_registers(sasm);
AddressLiteral dest(deopt_blob->unpack_with_reexecution());
__ jump_to(dest, O0);
__ delayed()->restore();
__ bind(no_deopt);
restore_live_registers(sasm);
__ ret();
__ delayed()->restore();
return oop_maps;
}
int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry_point, int number_of_arguments) {
// for sparc changing the number of arguments doesn't change
// anything about the frame size so we'll always lie and claim that
// we are only passing 1 argument.
set_num_rt_args(1);
assert_not_delayed();
// bang stack before going to runtime
set(-os::vm_page_size() + STACK_BIAS, G3_scratch);
st(G0, SP, G3_scratch);
// debugging support
assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
set_last_Java_frame(SP, noreg);
if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
save_thread(L7_thread_cache);
// do the call
call(entry_point, relocInfo::runtime_call_type);
if (!VerifyThread) {
delayed()->mov(G2_thread, O0); // pass thread as first argument
} else {
delayed()->nop(); // (thread already passed)
}
int call_offset = offset(); // offset of return address
restore_thread(L7_thread_cache);
reset_last_Java_frame();
// check for pending exceptions
{ Label L;
Address exception_addr(G2_thread, Thread::pending_exception_offset());
ld_ptr(exception_addr, Gtemp);
br_null_short(Gtemp, pt, L);
Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
st_ptr(G0, vm_result_addr);
Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
st_ptr(G0, vm_result_addr_2);
if (frame_size() == no_frame_size) {
// we use O7 linkage so that forward_exception_entry has the issuing PC
call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
delayed()->restore();
} else if (_stub_id == Runtime1::forward_exception_id) {
should_not_reach_here();
} else {
AddressLiteral exc(Runtime1::entry_for(Runtime1::forward_exception_id));
jump_to(exc, G4);
delayed()->nop();
}
bind(L);
}
// get oop result if there is one and reset the value in the thread
if (oop_result1->is_valid()) { // get oop result if there is one and reset it in the thread
get_vm_result (oop_result1);
} else {
// be a little paranoid and clear the result
Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
st_ptr(G0, vm_result_addr);
}
// get second result if there is one and reset the value in the thread
if (metadata_result->is_valid()) {
get_vm_result_2 (metadata_result);
} else {
// be a little paranoid and clear the result
Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
st_ptr(G0, vm_result_addr_2);
}
return call_offset;
}
// LP64 passes floating point arguments in F1, F3, F5, etc. instead of
// O0, O1, O2 etc..
// Doubles are passed in D0, D2, D4
// We store the signature of the first 16 arguments in the first argument
// slot because it will be overwritten prior to calling the native
// function, with the pointer to the JNIEnv.
// If LP64 there can be up to 16 floating point arguments in registers
// or 6 integer registers.
address AbstractInterpreterGenerator::generate_slow_signature_handler() {
enum {
non_float = 0,
float_sig = 1,
double_sig = 2,
sig_mask = 3
};
address entry = __ pc();
Argument argv(0, true);
// We are in the jni transition frame. Save the last_java_frame corresponding to the
// outer interpreter frame
//
__ set_last_Java_frame(FP, noreg);
// make sure the interpreter frame we've pushed has a valid return pc
__ mov(O7, I7);
__ mov(Lmethod, G3_scratch);
__ mov(Llocals, G4_scratch);
__ save_frame(0);
__ mov(G2_thread, L7_thread_cache);
__ add(argv.address_in_frame(), O3);
__ mov(G2_thread, O0);
__ mov(G3_scratch, O1);
__ call(CAST_FROM_FN_PTR(address, InterpreterRuntime::slow_signature_handler), relocInfo::runtime_call_type);
__ delayed()->mov(G4_scratch, O2);
__ mov(L7_thread_cache, G2_thread);
__ reset_last_Java_frame();
// load the register arguments (the C code packed them as varargs)
Address Sig = argv.address_in_frame(); // Argument 0 holds the signature
__ ld_ptr( Sig, G3_scratch ); // Get register argument signature word into G3_scratch
__ mov( G3_scratch, G4_scratch);
__ srl( G4_scratch, 2, G4_scratch); // Skip Arg 0
Label done;
for (Argument ldarg = argv.successor(); ldarg.is_float_register(); ldarg = ldarg.successor()) {
Label NonFloatArg;
Label LoadFloatArg;
Label LoadDoubleArg;
Label NextArg;
Address a = ldarg.address_in_frame();
__ andcc(G4_scratch, sig_mask, G3_scratch);
__ br(Assembler::zero, false, Assembler::pt, NonFloatArg);
__ delayed()->nop();
__ cmp(G3_scratch, float_sig );
__ br(Assembler::equal, false, Assembler::pt, LoadFloatArg);
__ delayed()->nop();
__ cmp(G3_scratch, double_sig );
__ br(Assembler::equal, false, Assembler::pt, LoadDoubleArg);
__ delayed()->nop();
__ bind(NonFloatArg);
// There are only 6 integer register arguments!
if ( ldarg.is_register() )
__ ld_ptr(ldarg.address_in_frame(), ldarg.as_register());
else {
// Optimization, see if there are any more args and get out prior to checking
// all 16 float registers. My guess is that this is rare.
// If is_register is false, then we are done the first six integer args.
__ br_null_short(G4_scratch, Assembler::pt, done);
}
__ ba(NextArg);
__ delayed()->srl( G4_scratch, 2, G4_scratch );
__ bind(LoadFloatArg);
__ ldf( FloatRegisterImpl::S, a, ldarg.as_float_register(), 4);
__ ba(NextArg);
__ delayed()->srl( G4_scratch, 2, G4_scratch );
__ bind(LoadDoubleArg);
__ ldf( FloatRegisterImpl::D, a, ldarg.as_double_register() );
__ ba(NextArg);
__ delayed()->srl( G4_scratch, 2, G4_scratch );
__ bind(NextArg);
}
__ bind(done);
__ ret();
__ delayed()->
restore(O0, 0, Lscratch); // caller's Lscratch gets the result handler
return entry;
}