/* * Broadcom specific IRQ setup */ void __init arch_init_irq(void) { int irq; //INTC->IrqMask = 0UL; //INTC->IrqStatus = 0UL; CPUINT1C->IntrW0MaskSet = 0xffffffff; CPUINT1C->IntrW1MaskSet = ~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK); change_c0_status(ST0_IE, ST0_IE); /* Setup timer interrupt */ irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0; irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1; irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type; /* Install all the 7xxx IRQs */ for (irq = 1; irq <= 32; irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = 0; irq_desc[irq].depth = 1; irq_desc[irq].chip = &brcm_intc_type; g_brcm_intc_cnt[irq -1] = 0; } for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = 0; irq_desc[irq].depth = 1; irq_desc[irq].chip = &brcm_intc_type; g_brcm_intc_cnt[irq -1] = 0; } /* Handle the Serial IRQs differently so they can have unique IRQs */ irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_UARTA_IRQ].action = 0; irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1; irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type; irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_UARTB_IRQ].action = 0; irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1; irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type; #ifdef CONFIG_OPROFILE /* profile IRQ */ irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED; irq_desc[BCM_PERFCOUNT_IRQ].action = 0; irq_desc[BCM_PERFCOUNT_IRQ].depth = 1; irq_desc[BCM_PERFCOUNT_IRQ].chip = &brcm_mips_performance_type; brcm_mips_performance_enable(0); #endif brcm_mips_int2_enable(0); }
static void brcm_mips_performance_end(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) brcm_mips_performance_enable(irq); }
static unsigned int brcm_mips_performance_startup(unsigned int irq) { brcm_mips_performance_enable(irq); return 0; /* never anything pending */ }
/* * Broadcom specific IRQ setup */ void __init brcm_irq_setup(void) { int irq; extern asmlinkage void brcmIRQ(void); //INTC->IrqMask = 0UL; //INTC->IrqStatus = 0UL; CPUINT1C->IntrW0MaskSet = 0xffffffff; CPUINT1C->IntrW1MaskSet = ~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK); set_except_vector(0, brcmIRQ); change_c0_status(ST0_IE, ST0_IE); /* Setup timer interrupt */ irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0; irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1; irq_desc[BCM_LINUX_SYSTIMER_IRQ].handler = &brcm_mips_int7_type; /* Install all the 7xxx IRQs */ #if 1 for (irq = 1; irq <= 32; irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = 0; irq_desc[irq].depth = 1; irq_desc[irq].handler = &brcm_intc_type; g_brcm_intc_cnt[irq -1] = 0; } for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = 0; irq_desc[irq].depth = 1; irq_desc[irq].handler = &brcm_intc_type; g_brcm_intc_cnt[irq -1] = 0; } #endif /* Handle the Serial IRQs differently so they can have unique IRQs */ irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_UARTA_IRQ].action = 0; irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1; irq_desc[BCM_LINUX_UARTA_IRQ].handler = &brcm_uart_type; #ifdef CONFIG_KGDB irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_UARTB_IRQ].action = 0; irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1; irq_desc[BCM_LINUX_UARTB_IRQ].handler = &brcm_uart_type; #endif #ifdef CONFIG_OPROFILE /* profile IRQ */ irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED; irq_desc[BCM_PERFCOUNT_IRQ].action = 0; irq_desc[BCM_PERFCOUNT_IRQ].depth = 1; irq_desc[BCM_PERFCOUNT_IRQ].handler = &brcm_mips_performance_type; brcm_mips_performance_enable(0); #endif brcm_mips_int2_enable(0); //enable the UPG level UARTA int. //*((volatile unsigned long*)BCHP_IRQ0_UARTA_IRQEN) |= BCHP_IRQ0_UARTA_IRQEN_uarta_MASK; }
/*! @brief Broadcom specific interrupt descriptors initialization. */ void __init brcm_irq_setup(void) { extern int noirqdebug; int irq; printk("timer irq %d end %d",BCM_LINUX_SYSTIMER_IRQ, BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_reserved0_SHIFT+32); //INTC->IrqMask = 0UL; //INTC->IrqStatus = 0UL; CPUINT1C->IntrW0MaskSet = 0xffffffff; CPUINT1C->IntrW1MaskSet = 0xffffffff; //~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK); change_c0_status(ST0_IE, 0); /* Setup timer interrupt */ irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0; irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1; irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type; /* Install all the 7xxx IRQs */ for (irq = 1; irq <= 32; irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = 0; irq_desc[irq].depth = 1; irq_desc[irq].chip = &brcm_intc_type; g_brcm_intc_cnt[irq -1] = 0; } for (irq = 32+1; irq <= 32+32; irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = 0; irq_desc[irq].depth = 1; irq_desc[irq].chip = &brcm_intc_type; g_brcm_intc_cnt[irq -1] = 0; } /* Handle the Serial IRQs differently so they can have unique IRQs */ irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_UARTA_IRQ].action = 0; irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1; irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type; irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_UARTB_IRQ].action = 0; irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1; irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type; #if 0 /* Set up smartcard interrupts. */ irq_desc[BCM_LINUX_SCA_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_SCA_IRQ].action = 0; irq_desc[BCM_LINUX_SCA_IRQ].depth = 1; irq_desc[BCM_LINUX_SCA_IRQ].chip = &brcm_intc_type; irq_desc[BCM_LINUX_SCB_IRQ].status = IRQ_DISABLED; irq_desc[BCM_LINUX_SCB_IRQ].action = 0; irq_desc[BCM_LINUX_SCB_IRQ].depth = 1; irq_desc[BCM_LINUX_SCB_IRQ].chip = &brcm_intc_type; #endif #ifdef CONFIG_OPROFILE /* profile IRQ */ irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED; irq_desc[BCM_PERFCOUNT_IRQ].action = 0; irq_desc[BCM_PERFCOUNT_IRQ].depth = 1; irq_desc[BCM_PERFCOUNT_IRQ].chip = &brcm_mips_performance_type; brcm_mips_performance_enable(0); #endif noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also). brcm_mips_int2_enable(0); }