__s32 drv_disp_init(void)
{
__disp_bsp_init_para para;
sunxi_pwm_init();
debug("====display init =====\n");
memset(¶, 0, sizeof(__disp_bsp_init_para));
#if (!defined CONFIG_ARCH_SUN7IW1P1)
para.reg_base[DISP_MOD_BE0] = SUNXI_DE_BE0_BASE;
para.reg_size[DISP_MOD_BE0] = 0x9fc;
para.reg_base[DISP_MOD_BE1] = SUNXI_DE_BE1_BASE;
para.reg_size[DISP_MOD_BE1] = 0x9fc;
para.reg_base[DISP_MOD_FE0] = SUNXI_DE_FE0_BASE;
para.reg_size[DISP_MOD_FE0] = 0x22c;
para.reg_base[DISP_MOD_FE1] = SUNXI_DE_FE1_BASE;
para.reg_size[DISP_MOD_FE1] = 0x22c;
para.reg_base[DISP_MOD_LCD0] = SUNXI_LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
para.reg_base[DISP_MOD_LCD1] = SUNXI_LCD1_BASE;
para.reg_size[DISP_MOD_LCD1] = 0x3fc;
para.reg_base[DISP_MOD_CCMU] = SUNXI_CCM_BASE;
para.reg_size[DISP_MOD_CCMU] = 0x2dc;
para.reg_base[DISP_MOD_PIOC] = SUNXI_PIO_BASE;
para.reg_size[DISP_MOD_PIOC] = 0x27c;
para.reg_base[DISP_MOD_PWM] = SUNXI_PWM_BASE;
para.reg_size[DISP_MOD_PWM] = 0x3c;
para.reg_base[DISP_MOD_DEU0] = SUNXI_DE_DEU0_BASE;
para.reg_size[DISP_MOD_DEU0] = 0x60;
para.reg_base[DISP_MOD_DEU1] = SUNXI_DE_DEU1_BASE;
para.reg_size[DISP_MOD_DEU1] = 0x60;
para.reg_base[DISP_MOD_CMU0] = SUNXI_DE_BE0_BASE;
para.reg_size[DISP_MOD_CMU0] = 0xfc;
para.reg_base[DISP_MOD_CMU1] = SUNXI_DE_BE1_BASE;
para.reg_size[DISP_MOD_CMU1] = 0xfc;
para.reg_base[DISP_MOD_DRC0] = SUNXI_DE_DRC0_BASE;
para.reg_size[DISP_MOD_DRC0] = 0xfc;
para.reg_base[DISP_MOD_DRC1] = SUNXI_DE_DRC1_BASE;
para.reg_size[DISP_MOD_DRC1] = 0xfc;
para.reg_base[DISP_MOD_DSI0] = SUNXI_MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
para.reg_base[DISP_MOD_DSI0_DPHY] = SUNXI_MIPI_DSI0_DPHY_BASE;
para.reg_size[DISP_MOD_DSI0_DPHY] = 0xfc;
para.reg_base[DISP_MOD_HDMI] = SUNXI_HDMI_BASE;
para.reg_size[DISP_MOD_HDMI] = 0x58c;
para.irq[DISP_MOD_BE0] = AW_IRQ_DEBE0;
para.irq[DISP_MOD_BE1] = AW_IRQ_DEBE1;
para.irq[DISP_MOD_FE0] = AW_IRQ_DEFE0;
para.irq[DISP_MOD_FE1] = AW_IRQ_DEFE1;
para.irq[DISP_MOD_DRC0] = AW_IRQ_DRC01;
para.irq[DISP_MOD_DRC1] = AW_IRQ_DEU01;
para.irq[DISP_MOD_LCD0] = AW_IRQ_LCD0;
para.irq[DISP_MOD_LCD1] = AW_IRQ_LCD1;
para.irq[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
#else
para.reg_base[DISP_MOD_BE0] = SUNXI_DE_BE0_BASE;
para.reg_size[DISP_MOD_BE0] = 0x5ff;
para.reg_base[DISP_MOD_BE1] = SUNXI_DE_BE1_BASE;
para.reg_size[DISP_MOD_BE1] = 0x5ff;
para.reg_base[DISP_MOD_FE0] = SUNXI_DE_FE0_BASE;
para.reg_size[DISP_MOD_FE0] = 0xa18;
para.reg_base[DISP_MOD_FE1] = SUNXI_DE_FE1_BASE;
para.reg_size[DISP_MOD_FE1] = 0xa18;
para.reg_base[DISP_MOD_LCD0] = SUNXI_LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x800;
para.reg_base[DISP_MOD_LCD1] = SUNXI_LCD1_BASE;
para.reg_size[DISP_MOD_LCD1] = 0x800;
para.reg_base[DISP_MOD_CCMU] = SUNXI_CCM_BASE;
para.reg_size[DISP_MOD_CCMU] = 0x2dc;
para.reg_base[DISP_MOD_PIOC] = SUNXI_PIO_BASE;
para.reg_size[DISP_MOD_PIOC] = 0x27c;
para.reg_base[DISP_MOD_PWM] = SUNXI_PWM_BASE;
para.reg_size[DISP_MOD_PWM] = 0x3c;
para.reg_base[DISP_MOD_HDMI] = SUNXI_HDMI_BASE;
para.reg_size[DISP_MOD_HDMI] = 0x580;
para.reg_base[DISP_MOD_TVE0] = SUNXI_TVE0_BASE;
para.reg_size[DISP_MOD_TVE0] = 0x20c;
para.irq[DISP_MOD_BE0] = AW_IRQ_DEBE0;
para.irq[DISP_MOD_BE1] = AW_IRQ_DEBE1;
para.irq[DISP_MOD_FE0] = AW_IRQ_DEFE0;
para.irq[DISP_MOD_FE1] = AW_IRQ_DEFE1;
para.irq[DISP_MOD_LCD0] = AW_IRQ_LCD0;
para.irq[DISP_MOD_LCD1] = AW_IRQ_LCD1;
#endif
para.disp_int_process = disp_int_process;
#if ((defined CONFIG_SUN6I) || (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN7IW1P1))
para.hdmi_open = DRV_hdmi_open;
para.hdmi_close = DRV_hdmi_close;
para.hdmi_set_mode = DRV_hdmi_set_display_mode;
para.hdmi_mode_support = DRV_hdmi_mode_support;
para.hdmi_get_HPD_status = DRV_hdmi_get_HPD_status;
para.hdmi_set_pll = DRV_hdmi_set_pll;
#endif
//para.hdmi_get_disp_func = disp_get_hdmi_func;
memset(&g_disp_drv, 0, sizeof(__disp_drv_t));
bsp_disp_init(¶);
#if ((defined CONFIG_SUN6I) || (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN7IW1P1))
Hdmi_set_reg_base(0x01c16000);
Hdmi_hal_init();
#endif
bsp_disp_open();
lcd_init();
#if 0
if(0)
{
__disp_color_t bk_color;
printf("====DRV_lcd_open before ====\n");
DRV_lcd_open(0);
printf("====DRV_lcd_open after ====\n");
bsp_disp_print_reg(1, DISP_MOD_PIOC);
bsp_disp_print_reg(1, DISP_MOD_PWM);
bsp_disp_print_reg(1, DISP_MOD_CCMU);
bsp_disp_print_reg(1, DISP_MOD_LCD0);
bsp_disp_lcd_set_src(0,DISP_LCDC_SRC_WHITE);
printf("====lcd_white_src ====\n");
__msdelay(1000);
*(__u32*)0x1c0c0f4 = 0xffff;
bsp_disp_print_reg(1, DISP_MOD_LCD0);
//bsp_disp_lcd_set_src(0,DISP_LCDC_SRC_BLACK);
//printf("====lcd_black_src ====\n");
//__msdelay(1000);
bsp_disp_print_reg(1, DISP_MOD_LCD0);
bsp_disp_lcd_set_src(0,DISP_LCDC_SRC_DE_CH1);
printf("====lcd_ch1_src ====\n");
__msdelay(1000);
bk_color.red = 0xff;
bk_color.green = 0x00;
bk_color.blue = 0x00;
bsp_disp_set_bk_color(0,&bk_color);
printf("==== red bk color ====\n");
__msdelay(1000);
return 0;
bk_color.red = 0x00;
bk_color.green = 0xff;
bk_color.blue = 0x00;
bsp_disp_set_bk_color(0,&bk_color);
printf("==== red green color ====\n");
__msdelay(1000);
bk_color.red = 0x00;
bk_color.green = 0x00;
bk_color.blue = 0xff;
bsp_disp_set_bk_color(0,&bk_color);
printf("==== red bk color ====\n");
__msdelay(1000);
}
printf("====display init end ====\n");
#endif
printf("DRV_DISP_Init: opened\n");
display_opens = 1;
return 0;
}
s32 drv_disp_init(void)
{
#ifdef CONFIG_FPGA
return 0;
#else
__disp_bsp_init_para para;
sunxi_pwm_init();
memset(¶, 0, sizeof(__disp_bsp_init_para));
#if defined(CONFIG_ARCH_SUN9IW1P1)
para.reg_base[DISP_MOD_BE0] = BE0_BASE;
para.reg_size[DISP_MOD_BE0] = 0x9fc;
para.reg_base[DISP_MOD_BE1] = BE1_BASE;
para.reg_size[DISP_MOD_BE1] = 0x9fc;
para.reg_base[DISP_MOD_BE2] = BE2_BASE;
para.reg_size[DISP_MOD_BE2] = 0x9fc;
para.reg_base[DISP_MOD_FE0] = FE0_BASE;
para.reg_size[DISP_MOD_FE0] = 0x22c;
para.reg_base[DISP_MOD_FE1] = FE1_BASE;
para.reg_size[DISP_MOD_FE1] = 0x22c;
para.reg_base[DISP_MOD_FE2] = FE2_BASE;
para.reg_size[DISP_MOD_FE2] = 0x22c;
para.reg_base[DISP_MOD_LCD0] = LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
para.reg_base[DISP_MOD_LCD1] = LCD1_BASE;
para.reg_size[DISP_MOD_LCD1] = 0x3fc;
para.reg_base[DISP_MOD_CCMU] = CCMPLL_BASE;
para.reg_size[DISP_MOD_CCMU] = 0x2dc;
para.reg_base[DISP_MOD_PIOC] = PIO_BASE;
para.reg_size[DISP_MOD_PIOC] = 0x27c;
para.reg_base[DISP_MOD_PWM] = PWM03_BASE;
para.reg_size[DISP_MOD_PWM] = 0x3c;
para.reg_base[DISP_MOD_DEU0] = DEU0_BASE;
para.reg_size[DISP_MOD_DEU0] = 0x60;
para.reg_base[DISP_MOD_DEU1] = DEU1_BASE;
para.reg_size[DISP_MOD_DEU1] = 0x60;
para.reg_base[DISP_MOD_CMU0] = BE0_BASE;
para.reg_size[DISP_MOD_CMU0] = 0xfc;
para.reg_base[DISP_MOD_CMU1] = BE1_BASE;
para.reg_size[DISP_MOD_CMU1] = 0xfc;
para.reg_base[DISP_MOD_DRC0] = DRC0_BASE;
para.reg_size[DISP_MOD_DRC0] = 0xfc;
para.reg_base[DISP_MOD_DRC1] = DRC1_BASE;
para.reg_size[DISP_MOD_DRC1] = 0xfc;
para.reg_base[DISP_MOD_DSI0] = MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
para.reg_base[DISP_MOD_DSI0_DPHY] = MIPI_DSI0_DPHY_BASE;
para.reg_size[DISP_MOD_DSI0_DPHY] = 0xfc;
para.reg_base[DISP_MOD_HDMI] = HDMI_BASE;
para.reg_size[DISP_MOD_HDMI] = 0xfc;
para.reg_base[DISP_MOD_TOP] = REGS_AHB2_BASE;
para.reg_size[DISP_MOD_TOP] = 0xfc;
para.irq_no[DISP_MOD_BE0] = AW_IRQ_DEBE0;
para.irq_no[DISP_MOD_BE1] = AW_IRQ_DEBE1;
para.irq_no[DISP_MOD_BE2] = AW_IRQ_DEBE2;
para.irq_no[DISP_MOD_FE0] = AW_IRQ_DEFE0;
para.irq_no[DISP_MOD_FE1] = AW_IRQ_DEFE1;
para.irq_no[DISP_MOD_DRC0] = AW_IRQ_DRC01;
para.irq_no[DISP_MOD_DRC1] = AW_IRQ_DEU01;
para.irq_no[DISP_MOD_LCD0] = AW_IRQ_LCD0;
para.irq_no[DISP_MOD_LCD1] = AW_IRQ_LCD1;
para.irq_no[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
para.irq_no[DISP_MOD_EDP] = AW_IRQ_EDP;
#elif defined(CONFIG_ARCH_SUN8IW5P1)
para.reg_base[DISP_MOD_BE0] = DEBE0_BASE;
para.reg_size[DISP_MOD_BE0] = 0xfc;
para.reg_base[DISP_MOD_FE0] = DEFE0_BASE;
para.reg_size[DISP_MOD_FE0] = 0x22c;
para.reg_base[DISP_MOD_LCD0] = LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
para.reg_base[DISP_MOD_DRC0] = DRC0_BASE;
para.reg_size[DISP_MOD_DRC0] = 0xfc;
para.reg_base[DISP_MOD_DSI0] = MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
para.reg_base[DISP_MOD_DSI0_DPHY] = MIPI_DSI0PHY_BASE;
para.reg_size[DISP_MOD_DSI0_DPHY] = 0xfc;
para.reg_base[DISP_MOD_CCMU] = CCM_BASE;
para.reg_size[DISP_MOD_CCMU] = 0x2dc;
para.reg_base[DISP_MOD_PIOC] = PIO_BASE;
para.reg_size[DISP_MOD_PIOC] = 0x27c;
para.reg_base[DISP_MOD_PWM] = PWM03_BASE;
para.reg_size[DISP_MOD_PWM] = 0x3c;
para.reg_base[DISP_MOD_WB0] = DRC0_BASE+ 0x200;
para.reg_size[DISP_MOD_WB0] = 0x2fc;
para.reg_base[DISP_MOD_SAT0] = SAT0_BASE;
para.reg_size[DISP_MOD_SAT0] = 0x2fc;
para.irq_no[DISP_MOD_BE0] = AW_IRQ_DEBE0;
para.irq_no[DISP_MOD_LCD0] = AW_IRQ_LCD0;
para.irq_no[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
#endif
memset(&g_disp_drv, 0, sizeof(disp_drv_info));
bsp_disp_init(¶);
#if (defined(CONFIG_ARCH_TV) && defined(CONFIG_ARCH_SUN9IW1P1))
gm7121_module_init();
#endif //#if defined(CONFIG_ARCH_TV)
#if ((defined CONFIG_SUN6I) || (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1))
Hdmi_init();
#endif
bsp_disp_open();
lcd_init();
init_flag = 1;
__inf("DRV_DISP_Init end\n");
return 0;
#endif
}
s32 drv_disp_init(void)
{
#ifdef CONFIG_FPGA
return 0;
#else
disp_bsp_init_para para;
int disp, num_screens;
drv_disp_check_spec();
sunxi_pwm_init();
disp_sys_clk_init();
memset(¶, 0, sizeof(disp_bsp_init_para));
para.reg_base[DISP_MOD_DE] = DE_BASE;
para.reg_size[DISP_MOD_DE] = DE_SIZE;
para.reg_base[DISP_MOD_LCD0] = LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
#ifdef DISP_DEVICE_NUM
#if DISP_DEVICE_NUM == 2
para.reg_base[DISP_MOD_LCD1] = LCD1_BASE;
para.reg_size[DISP_MOD_LCD1] = 0x3fc;
#endif
#else
# error "DEVICE_NUM undefined!"
#endif
#ifdef SUPPORT_DSI
para.reg_base[DISP_MOD_DSI0] = MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
#endif
para.irq_no[DISP_MOD_DE] = AW_IRQ_DEIRQ0;
para.irq_no[DISP_MOD_LCD0] = AW_IRQ_LCD0;
#if defined(DISP_DEVICE_NUM)
#if DISP_DEVICE_NUM == 2
para.irq_no[DISP_MOD_LCD1] = AW_IRQ_LCD1;
#endif
#else
# error "DEVICE_NUM undefined!"
#endif
#if defined(SUPPORT_DSI)
para.irq_no[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
#endif
memset(&g_disp_drv, 0, sizeof(disp_drv_info));
bsp_disp_init(¶);
num_screens = bsp_disp_feat_get_num_screens();
for(disp=0; disp<num_screens; disp++) {
g_disp_drv.mgr[disp] = disp_get_layer_manager(disp);
}
#if defined(SUPPORT_HDMI)
Hdmi_init();
#endif
#if defined(SUPPORT_TV)
tv_init();
#endif
#if defined(CONFIG_USE_AC200)
tv_ac200_init();
#endif
bsp_disp_open();
lcd_init();
#if defined(CVBS_MODE_USED_GM7121)
gm7121_module_init();
#endif
init_flag = 1;
printf("DRV_DISP_Init end\n");
return 0;
#endif
}
