/*---------------------------------------------------------------------------*
* Creatix / Teles PnP ISAC put fifo routine
*---------------------------------------------------------------------------*/
static void
ctxs0P_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
{
bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[what+2]);
bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[what+2]);
bus_space_write_multi_1(t,h,0x3e,buf,size);
}
/*---------------------------------------------------------------------------*
* AVM write fifo routine
*---------------------------------------------------------------------------*/
static void
avma1_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
{
bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[what+4]);
bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[what+4]);
bus_space_write_multi_1(t, h, 0, (u_int8_t*)buf, size);
}
static void
avma1_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[what+4].t;
bus_space_handle_t h = sc->sc_maps[what+4].h;
bus_space_write_multi_1(t, h, 0, (u_int8_t*)buf, size);
}
__stdcall static void
hal_writeport_buf_uchar(uint8_t *port, uint8_t *val, uint32_t cnt)
{
bus_space_write_multi_1(NDIS_BUS_SPACE_IO, 0x0,
(bus_size_t)port, val, cnt);
return;
}
static void
avma1_pcmcia_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
bus_space_write_1(t, h, ADDR_REG_OFFSET, what_map[what]);
bus_space_write_multi_1(t, h, DATA_REG_OFFSET, buf, size);
}
static void
tels0163_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[what+1].t;
bus_space_handle_t h = sc->sc_maps[what+1].h;
bus_size_t o = sc->sc_maps[what+1].offset;
bus_space_write_multi_1(t, h, o + 0x1e, buf, size);
}
static void
ctxs0P_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[what+1].t;
bus_space_handle_t h = sc->sc_maps[what+1].h;
bus_size_t o = sc->sc_maps[what+1].offset;
bus_space_write_multi_1(t, h, o + 0x3e, (u_int8_t*)buf, size);
}
static void dynalink_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ADDR, 0);
bus_space_write_multi_1(t, h, ISAC, buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ADDR, HSCXA);
bus_space_write_multi_1(t, h, HSCX, buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ADDR, HSCXB);
bus_space_write_multi_1(t, h, HSCX, buf, size);
break;
}
}
static void itkix1_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ITK_ALE, 0);
bus_space_write_multi_1(t, h, ITK_ISAC_DATA, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ITK_ALE, HSCXA);
bus_space_write_multi_1(t, h, ITK_HSCX_DATA, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ITK_ALE, HSCXB);
bus_space_write_multi_1(t, h, ITK_HSCX_DATA, (u_int8_t*)buf, size);
break;
}
}
static void
siemens_isurf_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_ISAC_OFF);
bus_space_write_multi_1(t, h, SIE_ISURF_OFF_RW, buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_HSCXA_OFF);
bus_space_write_multi_1(t, h, SIE_ISURF_OFF_RW, buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_HSCXB_OFF);
bus_space_write_multi_1(t, h, SIE_ISURF_OFF_RW, buf, size);
break;
}
}
static void
sws_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, SWS_RW, 0);
bus_space_write_multi_1(t, h, SWS_ISAC, buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, SWS_RW, 0);
bus_space_write_multi_1(t, h, SWS_HSCX0, buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, SWS_RW, 0x40);
bus_space_write_multi_1(t, h, SWS_HSCX0, buf, size);
break;
}
}
static void
dynalink_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
{
bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ADDR, 0);
bus_space_write_multi_1(t, h, ISAC, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ADDR, HSCXA);
bus_space_write_multi_1(t, h, HSCX, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ADDR, HSCXB);
bus_space_write_multi_1(t, h, HSCX, (u_int8_t*)buf, size);
break;
}
}
integrate void
clmpcc_wrtx_multi(struct clmpcc_softc *sc, u_int8_t *buff, u_int count)
{
u_int offset = CLMPCC_REG_TDR;
#if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
offset ^= (sc->sc_byteswap & 2);
#elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
#endif
bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count);
}
/*---------------------------------------------------------------------------*
* ELSA QuickStep 1000pro/ISA ISAC put fifo routine
*---------------------------------------------------------------------------*/
static void
eqs1pi_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
{
bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ELSA_OFF_OFF, 0);
bus_space_write_multi_1(t, h, ELSA_OFF_ISAC, buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ELSA_OFF_OFF, 0);
bus_space_write_multi_1(t, h, ELSA_OFF_HSCX, buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ELSA_OFF_OFF, 0x40);
bus_space_write_multi_1(t, h, ELSA_OFF_HSCX, buf, size);
break;
}
}
/*---------------------------------------------------------------------------*
* Eicon Diehl DIVA 2.02
*---------------------------------------------------------------------------*/
static void
diva_ipac_write_fifo(struct l1_softc *sc,int what,void *buf,size_t size)
{
bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
switch ( what )
{
case ISIC_WHAT_ISAC:
bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_ISAC_OFF);
bus_space_write_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_HSCXA_OFF);
bus_space_write_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_HSCXB_OFF);
bus_space_write_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
break;
}
}
/*---------------------------------------------------------------------------*
* AVM write fifo routines
*---------------------------------------------------------------------------*/
static void
avm_pnp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
{
bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, ISAC_FIFO);
bus_space_write_multi_1(btag, bhandle, ISAC_REG_OFFSET, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXA:
hscx_write_fifo(0, buf, size, sc);
break;
case ISIC_WHAT_HSCXB:
hscx_write_fifo(1, buf, size, sc);
break;
}
}
static inline void
__sscom_output_chunk(struct sscom_softc *sc, int ufstat)
{
int n, space;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
n = sc->sc_tbc;
space = 16 - __SHIFTOUT(ufstat, UFSTAT_TXCOUNT);
if (n > space)
n = space;
if (n > 0) {
bus_space_write_multi_1(iot, ioh, SSCOM_UTXH, sc->sc_tba, n);
sc->sc_tbc -= n;
sc->sc_tba += n;
}
}
u_char
ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
{
struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
switch (iop) {
case PPB_OUTSB_EPP:
bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
break;
case PPB_OUTSW_EPP:
bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
break;
case PPB_OUTSL_EPP:
bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
break;
case PPB_INSB_EPP:
bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
break;
case PPB_INSW_EPP:
bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
break;
case PPB_INSL_EPP:
bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
break;
case PPB_RDTR:
return (r_dtr(ppc));
case PPB_RSTR:
return (r_str(ppc));
case PPB_RCTR:
return (r_ctr(ppc));
case PPB_REPP_A:
return (r_epp_A(ppc));
case PPB_REPP_D:
return (r_epp_D(ppc));
case PPB_RECR:
return (r_ecr(ppc));
case PPB_RFIFO:
return (r_fifo(ppc));
case PPB_WDTR:
w_dtr(ppc, byte);
break;
case PPB_WSTR:
w_str(ppc, byte);
break;
case PPB_WCTR:
w_ctr(ppc, byte);
break;
case PPB_WEPP_A:
w_epp_A(ppc, byte);
break;
case PPB_WEPP_D:
w_epp_D(ppc, byte);
break;
case PPB_WECR:
w_ecr(ppc, byte);
break;
case PPB_WFIFO:
w_fifo(ppc, byte);
break;
default:
panic("%s: unknown I/O operation", __func__);
break;
}
return (0); /* not significative */
}
/*
* Reset multicast filter.
*/
void
qe_mcreset(struct qe_softc *sc)
{
struct ethercom *ec = &sc->sc_ethercom;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mr = sc->sc_mr;
struct ether_multi *enm;
struct ether_multistep step;
uint32_t crc;
uint16_t hash[4];
uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0];
int i;
#if defined(SUN4U) || defined(__GNUC__)
(void)&t;
#endif
/* We also enable transmitter & receiver here */
maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV;
if (ifp->if_flags & IFF_PROMISC) {
maccc |= QE_MR_MACCC_PROM;
bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
return;
}
if (ifp->if_flags & IFF_ALLMULTI) {
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
return;
}
hash[3] = hash[2] = hash[1] = hash[0] = 0;
ETHER_FIRST_MULTI(step, ec, enm);
while (enm != NULL) {
if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
ETHER_ADDR_LEN) != 0) {
/*
* We must listen to a range of multicast
* addresses. For now, just accept all
* multicasts, rather than trying to set only
* those filter bits needed to match the range.
* (At this time, the only use of address
* ranges is for IP multicast routing, for
* which the range is big enough to require
* all bits set.)
*/
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
ifp->if_flags |= IFF_ALLMULTI;
break;
}
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
crc >>= 26;
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
}
/* We need to byte-swap the hash before writing to the chip. */
for (i = 0; i < 7; i += 2) {
octet = ladrp[i];
ladrp[i] = ladrp[i + 1];
ladrp[i + 1] = octet;
}
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
}
void
qeinit(struct qe_softc *sc)
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t cr = sc->sc_cr;
bus_space_handle_t mr = sc->sc_mr;
struct qec_softc *qec = sc->sc_qec;
uint32_t qecaddr;
uint8_t *ea;
int s;
#if defined(SUN4U) || defined(__GNUC__)
(void)&t;
#endif
s = splnet();
qestop(sc);
/*
* Allocate descriptor ring and buffers
*/
qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ);
/* Channel registers: */
bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma);
bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma);
bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
qecaddr = sc->sc_channel * qec->sc_msize;
bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
/* MACE registers: */
bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
/*
* Mask MACE's receive interrupt, since we're being notified
* by the QEC after DMA completes.
*/
bus_space_write_1(t, mr, QE_MRI_IMR,
QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM);
bus_space_write_1(t, mr, QE_MRI_BIUCC,
QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS);
bus_space_write_1(t, mr, QE_MRI_FIFOFC,
QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 |
QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU);
bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
/*
* Station address
*/
ea = sc->sc_enaddr;
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR);
bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
/* Apply media settings */
qe_ifmedia_upd(ifp);
/*
* Clear Logical address filter
*/
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
/* Clear missed packet count (register cleared on read) */
(void)bus_space_read_1(t, mr, QE_MRI_MPC);
#if 0
/* test register: */
bus_space_write_1(t, mr, QE_MRI_UTR, 0);
#endif
/* Reset multicast filter */
qe_mcreset(sc);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
}
/*
* Bus write multiple operations.
*/
void
bs_through_bs_wm_1(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, const u_int8_t *addr, bus_size_t count)
{
bus_space_write_multi_1(t->bs_base, bsh, offset, addr, count);
}
static int
hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen,
uint8_t *data)
{
struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc;
bus_space_tag_t pdmat = sc->sc_pdmat;
bus_space_handle_t pdmah = sc->sc_pdmah;
int i, s, icmd, resid;
s = splbio();
icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK;
NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
resid = datalen;
if (hcsc_ready(ncr_sc) == 0)
goto interrupt;
if (resid > HCSC_TSIZE_OUT) {
/*
* Because of the chips DMA prefetch, phase changes
* etc, won't be detected until we have written at
* least one byte more. We pre-write 4 bytes so
* subsequent transfers will be aligned to a 4 byte
* boundary. Assuming disconects will only occur on
* block boundaries, we then correct for the pre-write
* when and if we get a phase change. If the chip had
* DMA byte counting hardware, the assumption would not
* be necessary.
*/
bus_space_write_multi_1(pdmat, pdmah, 0, data, 4);
data += 4;
resid -= 4;
for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) {
if (hcsc_ready(ncr_sc) == 0) {
resid += 4; /* Overshot */
goto interrupt;
}
bus_space_write_multi_1(pdmat, pdmah, 0, data,
HCSC_TSIZE_OUT);
data += HCSC_TSIZE_OUT;
}
if (hcsc_ready(ncr_sc) == 0) {
resid += 4; /* Overshot */
goto interrupt;
}
}
if (resid) {
bus_space_write_multi_1(pdmat, pdmah, 0, data, resid);
resid = 0;
}
for (i = TIMEOUT; i > 0; i--) {
if ((NCR5380_READ(ncr_sc, sci_csr)
& (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
!= SCI_CSR_DREQ)
break;
}
if (i != 0)
bus_space_write_1(pdmat, pdmah, 0, 0);
else
printf("%s: timeout waiting for final SCI_DSR_DREQ.\n",
device_xname(ncr_sc->sc_dev));
hcsc_wait_not_req(ncr_sc);
interrupt:
SCI_CLR_INTR(ncr_sc);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
splx(s);
return datalen - resid;
}
static void
wb_sdmmc_write_data(struct wb_softc *wb, uint8_t *data, int len)
{
bus_space_write_multi_1(wb->wb_iot, wb->wb_ioh, WB_SD_FIFO, data, len);
}
