s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf) { HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); HAL_VERSION *hal_ver = &HalData->VersionID; s32 ret = _FAIL; if (IS_81XXC(*hal_ver) || IS_8723_SERIES(*hal_ver) ||IS_92D(*hal_ver) ||IS_8188E(*hal_ver)) { ret = c2h_evt_read(adapter, buf); } else if(IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver)) { ret = c2h_evt_read_88xx(adapter, buf); } else { rtw_warn_on(1); } return ret; }
void sd_int_dpc(PADAPTER padapter) { HAL_DATA_TYPE *phal; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); phal = GET_HAL_DATA(padapter); if (phal->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; #ifdef CONFIG_LPS_RPWM_TIMER u8 bcancelled; _cancel_timer(&padapter->pwrctrlpriv.pwr_rpwm_timer, &bcancelled); #endif // CONFIG_LPS_RPWM_TIMER _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); #endif } if (phal->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(&dvobj->intf_data, addr, 4, status); _sd_write(&dvobj->intf_data, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); rtw_mfree(status, 4); } else { DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } if (phal->sdio_hisr & SDIO_HISR_TXBCNOK) { DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_TXBCNERR) { DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_C2HCMD) { struct c2h_evt_hdr *c2h_evt; if ((c2h_evt = (struct c2h_evt_hdr *)rtw_zmalloc(16)) != NULL) { if (c2h_evt_read(padapter, (u8 *)c2h_evt) == _SUCCESS) { if (c2h_id_filter_ccx_8723a(c2h_evt->id)) { /* Handle CCX report here */ rtw_hal_c2h_handler(padapter, c2h_evt); rtw_mfree((u8*)c2h_evt, 16); } else { rtw_c2h_wk_cmd(padapter, (u8 *)c2h_evt); } } else { rtw_mfree((u8*)c2h_evt, 16); } } else { /* Error handling for malloc fail */ if (rtw_cbuf_push(padapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) DBG_871X("%s rtw_cbuf_push fail\n", __func__); _set_workitem(&padapter->evtpriv.c2h_wk); } } if (phal->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; u16 val=0; // DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); phal->sdio_hisr ^= SDIO_HISR_RX_REQUEST; do{ if (phal->SdioRxFIFOSize == 0) { _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 2, (u8*)&val); phal->SdioRxFIFOSize = le16_to_cpu(val); DBG_8192C("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, phal->SdioRxFIFOSize); } if (phal->SdioRxFIFOSize != 0) { #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, phal->SdioRxFIFOSize); #else precvbuf = sd_recv_rxfifo(padapter, phal->SdioRxFIFOSize); if (precvbuf) sd_rxhandler(padapter, precvbuf); else break; #endif } _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 2, (u8*)&val); phal->SdioRxFIFOSize = le16_to_cpu(val); }while(phal->SdioRxFIFOSize !=0); } }