s32 edma2_stress_test_stop()
{
set_test_switch_stat(EDMAC, TEST_STOP);
while(OK == taskIdVerify(g_edma2_busstress_info.edma_stress_test_task_id))
{
taskDelay(100);
}
if (NULL != g_edma2_busstress_info.edma_send_sem)
{
/*sema_delete(g_edma2_busstress_info.edma_send_sem);*/
semDelete(g_edma2_busstress_info.edma_send_sem);
}
bsp_softtimer_delete_sync(&g_edma2_busstress_info.edma_softtimer_list);
bsp_softtimer_free(&g_edma2_busstress_info.edma_softtimer_list);
cacheDmaFree(g_edma2_busstress_info.stDMATaskHandle[0].u32SrcAddr);
cacheDmaFree(g_edma2_busstress_info.stDMATaskHandle[0].u32DstAddr);
cacheDmaFree(g_edma2_busstress_info.stDMATaskHandle[1].u32SrcAddr);
cacheDmaFree(g_edma2_busstress_info.stDMATaskHandle[3].u32DstAddr);
return OK;
}
void
ssh_kernel_free(void *ptr)
{
SshUInt32 v = ((SshUInt32 *)ptr)[-1];
SSH_ASSERT(v == SSH_VX_KERNEL_ALLOC_DMA || v == 0);
if (v == SSH_VX_KERNEL_ALLOC_DMA)
cacheDmaFree((unsigned char *) ptr - SSH_MALLOC_OVERHEAD);
else
free((unsigned char *) ptr - SSH_MALLOC_OVERHEAD);
}
void
_tx_dv_free(int unit, dv_t *dv)
{
logMsg("dv_free!\n", 1, 2, 3, 4, 5, 6); /* DEL_ME */
if (dv) {
void *p = ((dcb12_t *)SOC_DCB_IDX2PTR(dv->dv_unit, dv->dv_dcb, 0))->addr;
if (p != NULL) {
cacheDmaFree(p);
}
soc_dma_dv_free(unit, dv);
}
}
LOCAL STATUS
NetdrvSend(END_DEVICE * pDrvCtrl, M_BLK_ID pMblk)
{
unsigned char *pucPktData=NULL;
uint32 len = 0;
uint32 ulPort = -1;
ULONG ulRet=OK;
unsigned int unit = 0;
int i;
/* taskDelay(0); */
#ifdef BOOTROM_DEBUG
PRINTF_DEBUG2("NetdrvSend\n"); /* DEL_ME */
#endif
/* END_TX_SEM_TAKE(&pDrvCtrl->end, WAIT_FOREVER); */
if (pMblk->mBlkPktHdr.len > NETDRV_CL_LEN - 4) {
ulRet = ERROR;
goto sendErr;
}
pucPktData = sal_dma_alloc(NETDRV_CL_LEN, "pucPktData");
if (NULL==pucPktData) {
ulRet = ERROR;
goto sendErr;
}
/* memset(pucPktData, 0, NETDRV_CL_LEN); */
len = (ULONG)netMblkToBufCopy(pMblk, pucPktData, NULL);
len = max(ETHERSMALL, len);
for (unit = 0; unit < _n_devices; unit++) {
if (pkt_bcm_tx(unit, pucPktData, len) != 0) { /* Synchronous TX */
printf("ERROR: fail to tx pkt unit %d\n", unit);
ulRet = ERROR;
goto sendErr;
}
}
g_ulPktSend++;
sendErr:
netMblkClChainFree (pMblk);
/* for the packet already sending, we don't want to free them */
if (NULL!=pucPktData) {
cacheDmaFree(pucPktData);
pucPktData = NULL;
}
/* END_TX_SEM_GIVE(&pDrvCtrl->end); */
/* Bump the statistic counter. */
END_ERR_ADD (&pDrvCtrl->end, MIB2_OUT_UCAST, +1);
return ulRet;
}
void
osl_dma_free_consistent(void *dev, uint size, void *va, void *pa)
{
cacheDmaFree(va);
}
s32 edma_test(enum edma_req_id req_id, u32 size, u32 bst_width,u32 bst_len, s32 vec_flag)
{
s32 chan_id = -1;
u32 index_size = 0;
u32 addr_use1 = 0;
u32 addr_use2 = 0;
u32 * temp = 0;
//bsp_edma_init();
if(0 == (addr1 = (u32*)cacheDmaMalloc(size+32)))
{
hiedmac_trace(BSP_LOG_LEVEL_DEBUG," malloc1 size=0x%x failed \n",size);
return -1;
}
if(0 == (addr2 = (u32*)cacheDmaMalloc(size+32)))
{
free(addr1);
hiedmac_trace(BSP_LOG_LEVEL_DEBUG," malloc2 size=0x%x failed \n",size);
return -1;
}
printf("addr1=0x%x, addr2=0x%x \n",(u32)addr1,(u32)addr2);
edma_build_data((u8*)addr1, size+32, 0x20);
edma_build_data((u8*)addr2, size+32, 0x40);
/*test: 让addr 1k 对齐 */
addr_use1 = (u32)addr1+4;
addr_use2 = (u32)addr2+4;
printf("addr_use1=0x%x, addr_use2=0x%x \n",addr_use1,addr_use2);
temp = (u32*)addr_use1;
for(index_size=0; index_size<(size/4);index_size++ )
{
*temp++ = (u32)index_size;
}
chan_id = bsp_edma_channel_init(req_id,0,0,0);
bsp_edma_channel_set_config(chan_id,3,bst_width,bst_len);
if(1==vec_flag)
{
bsp_edma_channel_start(chan_id, addr_use1, addr_use2 , size );
}
else
{
bsp_edma_channel_2vec_start(chan_id, addr_use1, addr_use2 , size,edma_align_size);
}
while( EDMA_CHN_BUSY == bsp_edma_channel_is_idle(chan_id) )
{
printf("a");
chan_stop++;
if (20==chan_stop)
{
bsp_edma_channel_stop( chan_id);
printf("A");
}
}
printf("a\n");
bsp_edma_channel_free(chan_id);
hiedmac_trace(BSP_LOG_LEVEL_DEBUG, "CMP after edma tranfer:%d \n",memcmp((void*)addr_use1,(void*)addr_use2,size));
hiedmac_trace(BSP_LOG_LEVEL_DEBUG, "CMP size+4 after edma :%d \n",memcmp((void*)addr_use1,(void*)addr_use2,size+4));
cacheDmaFree(addr1);
cacheDmaFree(addr2);
return 0;
}
void dma_free_coherent(void* none, u32 size, void *cpu_addr, edma_addr_t handle)
{
cacheDmaFree(cpu_addr);
}
void
osl_dma_free_consistent(osl_t *osh, unsigned int size, void *va, ulong pa)
{
cacheDmaFree(va);
}
/*
***************************************************************************
*Function: acquire
*Description: This routine is the ACQUIRE example program.
***************************************************************************
*/
void acquire(void)
{
char sbTopName[20],sbBotName[20];
FILE *ptrTopFile=0,*ptrBotFile=0;
unsigned int p6256RegBaseAddr[4]; /* For ALL 4 VIM sites */
P6256_BOARD_PARAMS p6256BoardParams[4];
P6256_REG_ADDR p6256Regs[4];
volatile int wdCount,wdCtrlWord;
unsigned int clockRate;
unsigned int numCyclesDelay,bifoClock;
printf("[acquire]:\tstarting\n");
/* Turn all led's off */
sysLED_Off(0);
sysLED_Off(1);
sysLED_Off(2);
sysLED_Off(3);
top_outData=(int *)cacheDmaMalloc(BUFFER_SIZE*sizeof(int));
bot_outData=(int *)cacheDmaMalloc(BUFFER_SIZE*sizeof(int));
top_iData= (int *)cacheDmaMalloc(BUFFER_SIZE*sizeof(int));
bot_iData= (int *)cacheDmaMalloc(BUFFER_SIZE*sizeof(int));
if(top_outData==0||top_iData==0||bot_outData==0||bot_iData==0)
{
sysLED_On(0);
fprintf(stderr,"[acquire] Unable to allocate data buffers\n");
return;
}
/* get module id; if module is not a 6256, exit */
if(sysVimGetModuleId(TOP_VIM_ID)!=P6256_MODULE_ID)
{
sysLED_On(0);
fprintf(stderr,"[acquire] unable to id 6256\n");
return;
}
/* Reset and Release All VIM sites */
*P4205_RESET_REG=P4205_RESET_VIM_ALL;
taskDelay(4);
*P4205_RESET_REG=0;
/* Assign the 6256 register base addresses For the selected Vim Site */
p6256RegBaseAddr[TOP_VIM_ID]=sysVimCtrlBase(TOP_VIM_ID);
p6256RegBaseAddr[BOT_VIM_ID]=sysVimCtrlBase(BOT_VIM_ID);
/* Initialize the 6256 using library routines ------------------ */
/* Initialize Table of 6256 Addresses for Top and Bottom VIMs */
P6256InitRegAddr(p6256RegBaseAddr[TOP_VIM_ID],&p6256Regs[TOP_VIM_ID]);
P6256InitRegAddr(p6256RegBaseAddr[BOT_VIM_ID],&p6256Regs[BOT_VIM_ID]);
/* Reset Board Registers for Top and Bottom VIMs */
P6256ResetRegs(&p6256Regs[TOP_VIM_ID]);
P6256ResetRegs(&p6256Regs[BOT_VIM_ID]);
/* Load board parameters with default values for Top and Bottom VIMs */
P6256SetBoardDefaults(&p6256BoardParams[TOP_VIM_ID]);
P6256SetBoardDefaults(&p6256BoardParams[BOT_VIM_ID]);
/*
*Apply program parameters to board parameters Parameters for both will
*be set in this local function
*/
P6256SetBoardParams(&p6256BoardParams[0]);
/*
* If the onboard clock is used, set clock rate for the default internal
* clock rate. If not, use the locally defined external clock rate.
* The external clock rate is also used when the clock is obtained from
* the sync bus, even if the sync bus is driven from the onboard clock.
* Note that the SAME Clock source will be used for BOTH Top and Bottom
* VIM Sites.
*/
if((p6256BoardParams[TOP_VIM_ID].clockSourceSelect==P6256_CLK_SRC_SEL_BYPASS)&&(p6256BoardParams[TOP_VIM_ID].clockSelect==P6256_ONBOARD_CLOCK))
clockRate = P6256_INT_OSC_STANDARD; /* defined in 6256.h */
else
clockRate = EXTERNAL_CLOCK_RATE; /* local define */
/* Initialize Board Registers */
P6256InitBoardRegs(&p6256BoardParams[TOP_VIM_ID],&p6256Regs[TOP_VIM_ID]);
P6256InitBoardRegs(&p6256BoardParams[BOT_VIM_ID],&p6256Regs[BOT_VIM_ID]);
/*
*******************************************************************
* DATA COLLECTION AND PROCESSING STAGE
*
* the data is channeled into buffers based on the data routing mode
* as set in the channel control register.
*******************************************************************
*/
/* Disable Fifo Writes */
P6256_DISABLE_FIFO_WRITE(p6256Regs[TOP_VIM_ID].syncGateGenerator);
P6256_DISABLE_FIFO_WRITE(p6256Regs[BOT_VIM_ID].syncGateGenerator);
wdCtrlWord=func_initialize_9656_dma_controller();
/* Calculate Slowest Bifo Clock */
bifoClock=25000000;
numCyclesDelay=sysGetCpuRate()/(bifoClock>>2);
/* Flush the Bifo */
sysVimFlushBifo(Delay,numCyclesDelay,512,16,512,16,TOP_VIM_ID);
sysVimFlushBifo(Delay,numCyclesDelay,512,16,512,16,BOT_VIM_ID);
/*fetch the data*/
/* Enable Fifo Writes */
P6256_ENABLE_FIFO_WRITE(p6256Regs[TOP_VIM_ID].syncGateGenerator);
P6256_ENABLE_FIFO_WRITE(p6256Regs[BOT_VIM_ID].syncGateGenerator);
/* Start both DMAs */
PLX9656_REG_WRITE(plx9656Base,PLX9656_PCI_DMACSR0_DMACSR1,wdCtrlWord);
/* Wait until done */
if(TOP_VIM_ID==P4205_VIM_A) /* upper VIM location, sites A & B */
{
while (!(GT_GPP_POLL_CAUSE(PLX_1_INT)))
;
GT_GPP_CLEAR_CAUSE(PLX_1_INT);
}
else
{
while (!(GT_GPP_POLL_CAUSE(PLX_2_INT)))
;
GT_GPP_CLEAR_CAUSE(PLX_2_INT);
}
/*sync with cache ... maybe unnecessary*/
cacheInvalidate(DATA_CACHE,(void *)top_outData,BUFFER_SIZE*sizeof(int));
cacheInvalidate(DATA_CACHE,(void *)bot_outData,BUFFER_SIZE*sizeof(int));
cacheInvalidate(DATA_CACHE,(void *)top_iData, BUFFER_SIZE*sizeof(int));
cacheInvalidate(DATA_CACHE,(void *)bot_iData, BUFFER_SIZE*sizeof(int));
/* strip out inphase/quadrature components*/
func_process_collected_data();
cacheFlush(DATA_CACHE,(void *)top_iData,BUFFER_SIZE*sizeof(int));
cacheFlush(DATA_CACHE,(void *)bot_iData,BUFFER_SIZE*sizeof(int));
/*create unique name for output files*/
sprintf(sbTopName,"./top%d.dat",TOP_VIM_ID);
sprintf(sbBotName,"./bot%d.dat",BOT_VIM_ID);
sbTopName[12]=0;
sbBotName[12]=0;
/*open/create file*/
ptrTopFile=fopen(sbTopName,"w");
ptrBotFile=fopen(sbBotName,"w");
if(ptrTopFile<=0||ptrBotFile<=0)
fprintf(stdout,"unable to create/open output file(s)\n");
else
{
/*write to file*/
for(wdCount=0;wdCount<BUFFER_SIZE;wdCount++)
{
fprintf(ptrTopFile,"%d\n",top_iData[wdCount]);
fprintf(ptrBotFile,"%d\n",bot_iData[wdCount]);
}
fclose(ptrTopFile);
fclose(ptrBotFile);
}
sysLED_On(1);
sysLED_On(2);
sysLED_On(3);
printf("[acquire]:\tconcluding\n");
/*free allocated resources and exit*/
cacheDmaFree((void *)top_outData);
cacheDmaFree((void *)bot_outData);
cacheDmaFree((void *)top_iData);
cacheDmaFree((void *)bot_iData);
}
