static int cell_spu_pc_collection(int cpu) { u32 trace_addr; int entry; /* process the collected SPU PC for the node */ entry = 0; trace_addr = cbe_read_pm(cpu, trace_address); while (!(trace_addr & CBE_PM_TRACE_BUF_EMPTY)) { /* there is data in the trace buffer to process */ spu_pc_extract(cpu, entry); entry++; if (entry >= TRACE_ARRAY_SIZE) /* spu_samples is full */ break; trace_addr = cbe_read_pm(cpu, trace_address); } return entry; }
static int cell_spu_pc_collection(int cpu) { u32 trace_addr; int entry; entry = 0; trace_addr = cbe_read_pm(cpu, trace_address); while (!(trace_addr & CBE_PM_TRACE_BUF_EMPTY)) { spu_pc_extract(cpu, entry); entry++; if (entry >= TRACE_ARRAY_SIZE) break; trace_addr = cbe_read_pm(cpu, trace_address); } return entry; }
void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) { struct cbe_pmd_shadow_regs *shadow_regs; u32 pm_ctrl; if (phys_ctr < NR_PHYS_CTRS) { /* Writing to a counter only writes to a hardware latch. * The new value is not propagated to the actual counter * until the performance monitor is enabled. */ WRITE_WO_MMIO(pm_ctr[phys_ctr], val); pm_ctrl = cbe_read_pm(cpu, pm_control); if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) { /* The counters are already active, so we need to * rewrite the pm_control register to "re-enable" * the PMU. */ cbe_write_pm(cpu, pm_control, pm_ctrl); } else { shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); shadow_regs->counter_value_in_latch |= (1 << phys_ctr); } } }
void cbe_enable_pm(u32 cpu) { struct cbe_pmd_shadow_regs *shadow_regs; u32 pm_ctrl; shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); shadow_regs->counter_value_in_latch = 0; pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON; cbe_write_pm(cpu, pm_control, pm_ctrl); }
u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr) { u32 pm_ctrl, size = 0; if (phys_ctr < NR_PHYS_CTRS) { pm_ctrl = cbe_read_pm(cpu, pm_control); size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32; } return size; }
void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size) { u32 pm_ctrl; if (phys_ctr < NR_PHYS_CTRS) { pm_ctrl = cbe_read_pm(cpu, pm_control); switch (ctr_size) { case 16: pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr); break; case 32: pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr); break; } cbe_write_pm(cpu, pm_control, pm_ctrl); } }
u32 cbe_get_and_clear_pm_interrupts(u32 cpu) { /* Reading pm_status clears the interrupt bits. */ return cbe_read_pm(cpu, pm_status); }
void cbe_disable_pm(u32 cpu) { u32 pm_ctrl; pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON; cbe_write_pm(cpu, pm_control, pm_ctrl); }