void ccdc_reset()
{
int i;
/* disable CCDC */
ccdc_enable(0);
/* set all registers to default value */
for (i = 0; i <= 0x94; i += 4) {
regw(0, i);
}
regw(0, PCR);
regw(0, SYN_MODE);
regw(0, HD_VD_WID);
regw(0, PIX_LINES);
regw(0, HORZ_INFO);
regw(0, VERT_START);
regw(0, VERT_LINES);
regw(0xffff00ff, CULLING);
regw(0, HSIZE_OFF);
regw(0, SDOFST);
regw(0, SDR_ADDR);
regw(0, VDINT);
regw(0, REC656IF);
regw(0, CCDCFG);
regw(0, FMTCFG);
regw(0, VP_OUT);
}
static void ccdc_reset(void)
{
int i, clkctrl;
/* disable CCDC */
printk(KERN_DEBUG "\nstarting ccdc_reset...");
ccdc_enable(0);
/* set all registers to default value */
for (i = 0; i <= 0x15c; i += 4)
regw(0, i);
/* no culling support */
regw(0xffff, CULH);
regw(0xff, CULV);
/* Set default Gain and Offset */
ccdc_hw_params_raw.gain.r_ye = 256;
ccdc_hw_params_raw.gain.gb_g = 256;
ccdc_hw_params_raw.gain.gr_cy = 256;
ccdc_hw_params_raw.gain.b_mg = 256;
ccdc_hw_params_raw.ccdc_offset = 0;
ccdc_config_gain_offset();
/* up to 12 bit sensor */
regw(0x0FFF, OUTCLIP);
vpss_dfc_memory_sel(VPSS_DFC_SEL_IPIPE);
regw_bl(0x00, CCDCMUX); /*CCDC input Mux select directly from sensor */
clkctrl = regr_bl(CLKCTRL);
clkctrl &= 0x3f;
clkctrl |= 0x40;
regw_bl(clkctrl, CLKCTRL);
printk(KERN_DEBUG "\nEnd of ccdc_reset...");
}
