void CALLBACK cdvdDmaInterrupt(s32 channel)
{
#ifdef ENABLE_NEW_IOPDMA_CDVD
cdrInterrupt();
#endif
}
void psxBranchTest() {
if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
psxRcntUpdate();
if (psxRegs.interrupt) {
if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_SIO);
sioInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDR);
cdrInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
cdrReadInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
gpuInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
mdec1Interrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
spuInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
mdec0Interrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
gpuotcInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
cdrDmaInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRPLAY)) { // cdr play timing
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRPLAY].sCycle) >= psxRegs.intCycle[PSXINT_CDRPLAY].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRPLAY);
cdrPlayInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRDBUF)) { // cdr decoded buffer
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDBUF].sCycle) >= psxRegs.intCycle[PSXINT_CDRDBUF].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRDBUF);
cdrDecodedBufferInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
cdrLidSeekInterrupt();
}
}
}
if (psxHu32(0x1070) & psxHu32(0x1074)) {
if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
#ifdef PSXCPU_LOG
PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
#endif
psxException(0x400, 0);
}
}
}
