/****************************************************************************
*
* Function Name: CHAL_HANDLE chal_caph_dma_init(cUInt32 baseAddress)
*
* Description: init CAPH DMA block
*
****************************************************************************/
CHAL_HANDLE chal_caph_dma_init(cUInt32 baseAddress)
{
cUInt8 ch;
/* Go through all the channels and set them not allocated */
for (ch = 0; ch < CHAL_CAPH_DMA_MAX_CHANNELS; ch++)
chal_caph_dma_cb.alloc_status[ch] = FALSE;
/* Set the register base address to the caller supplied base address */
chal_caph_dma_cb.base = baseAddress;
chal_caph_dma_funcs.set_hibuffer = chal_caph_dma_default_set_hibuffer;
chal_caph_dma_platform_init(&chal_caph_dma_funcs);
/* Initialize AADMAC wrap size for all channels, any number greater than
1 is fine */
{
CHAL_HANDLE handle = (CHAL_HANDLE) (&chal_caph_dma_cb);
CAPH_DMA_CHANNEL_e caph_aadmac_ch;
for (ch = 0; ch < CHAL_CAPH_DMA_MAX_CHANNELS; ch++) {
caph_aadmac_ch = (CAPH_DMA_CHANNEL_e) (1UL << ch);
chal_caph_dma_set_buffer(handle, caph_aadmac_ch, 0,
0x100);
}
}
return (CHAL_HANDLE) (&chal_caph_dma_cb);
}
/****************************************************************************
*
* Function Name: void csl_caph_dma_switch_buffer(CSL_CAPH_DMA_CONFIG_t
* chnl_config)
*
* Description: switch DMA to access another memory buffer.
*
****************************************************************************/
void csl_caph_dma_switch_buffer(CSL_CAPH_DMA_CONFIG_t chnl_config)
{
CAPH_DMA_CHANNEL_e caph_aadmac_ch = CAPH_DMA_CH_VOID;
CAPH_CFIFO_e caph_cfifo_fifo = CAPH_CFIFO_VOID;
CAPH_CFIFO_CHNL_DIRECTION_e direction = CAPH_CFIFO_IN;
aTrace(LOG_AUDIO_CSL, "%s::\n", __func__);
if ((chnl_config.fifo == CSL_CAPH_CFIFO_NONE)
|| (chnl_config.dma_ch == CSL_CAPH_DMA_NONE))
return;
caph_aadmac_ch = csl_caph_dma_get_chal_chnl(chnl_config.dma_ch);
caph_cfifo_fifo = csl_caph_cfifo_get_chal_fifo(chnl_config.fifo);
chal_caph_dma_set_cfifo(handle, caph_aadmac_ch, caph_cfifo_fifo);
direction = csl_caph_dma_get_chal_direction(chnl_config.direction);
chal_caph_dma_set_direction(handle, caph_aadmac_ch, direction);
chal_caph_dma_set_buffer(handle, caph_aadmac_ch,
(cUInt32) (chnl_config.mem_addr),
chnl_config.mem_size);
chal_caph_dma_set_tsize(handle, caph_aadmac_ch, chnl_config.Tsize);
chal_caph_dma_set_ddrfifo_status(handle, caph_aadmac_ch,
CAPH_READY_HIGHLOW);
chal_caph_dma_clr_channel_fifo(handle, caph_aadmac_ch);
dmaCH_ctrl[chnl_config.dma_ch].caphDmaCb = chnl_config.dmaCB;
csl_caph_dma_start_transfer(chnl_config.dma_ch);
return;
}
/****************************************************************************
*
* Function Name:void csl_caph_dma_config_channel(CSL_CAPH_DMA_CONFIG_t
* chnl_config)
*
* Description: assign and configure CAPH DMA channel
*
****************************************************************************/
void csl_caph_dma_config_channel(CSL_CAPH_DMA_CONFIG_t chnl_config)
{
CAPH_DMA_CHANNEL_e caph_aadmac_ch = CAPH_DMA_CH_VOID;
CAPH_CFIFO_e caph_cfifo_fifo = CAPH_CFIFO_VOID;
CAPH_CFIFO_CHNL_DIRECTION_e direction = CAPH_CFIFO_IN;
aTrace(LOG_AUDIO_CSL,
"%s::dir %d fifo %d dma %d mem %p size %ld Tsize %d dmaCB %p "
"n_dma_buf %d dma_buf_size %d\n",
__func__,
chnl_config.direction, chnl_config.fifo,
chnl_config.dma_ch, chnl_config.mem_addr,
chnl_config.mem_size, chnl_config.Tsize,
chnl_config.dmaCB,
chnl_config.n_dma_buf,
chnl_config.dma_buf_size);
if ((chnl_config.fifo == CSL_CAPH_CFIFO_NONE)
|| (chnl_config.dma_ch == CSL_CAPH_DMA_NONE))
return;
caph_aadmac_ch = csl_caph_dma_get_chal_chnl(chnl_config.dma_ch);
caph_cfifo_fifo = csl_caph_cfifo_get_chal_fifo(chnl_config.fifo);
chal_caph_dma_clear_register(handle, caph_aadmac_ch);
chal_caph_dma_set_cfifo(handle, caph_aadmac_ch, caph_cfifo_fifo);
direction = csl_caph_dma_get_chal_direction(chnl_config.direction);
chal_caph_dma_set_direction(handle, caph_aadmac_ch, direction);
chal_caph_dma_set_buffer(handle, caph_aadmac_ch,
(cUInt32) (chnl_config.mem_addr),
chnl_config.mem_size);
chal_caph_dma_set_tsize(handle, caph_aadmac_ch, chnl_config.Tsize);
/*On B1, FIFO_RST will clear SW_RDY bits*/
if (cpu_is_rhea_B0()) {
chal_caph_dma_set_ddrfifo_status(handle, caph_aadmac_ch,
CAPH_READY_HIGHLOW);
chal_caph_dma_clr_channel_fifo(handle, caph_aadmac_ch);
} else {
chal_caph_dma_clr_channel_fifo(handle, caph_aadmac_ch);
chal_caph_dma_set_ddrfifo_status(handle, caph_aadmac_ch,
CAPH_READY_HIGHLOW);
}
dmaCH_ctrl[chnl_config.dma_ch].caphDmaCb = chnl_config.dmaCB;
if (chnl_config.n_dma_buf) {
chal_caph_dma_set_hibuffer(handle, caph_aadmac_ch,
(cUInt32) (chnl_config.mem_addr + chnl_config.dma_buf_size),
0);
chal_caph_dma_en_hibuffer(handle, caph_aadmac_ch);
}
return;
}
