Ejemplo n.º 1
0
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;
  SI val;

  check_desc (sd);

  if (!check_regno (regno))
    return -1;

  size = reg_size (regno);

  if (length != size)
    return -1;

  val = get_le (buf, length);

  if (regno == sim_rl78_pc_regnum)
    {
      pc = val;

      /* The rl78 program counter is 20 bits wide.  Ensure that GDB
         hasn't picked up any stray bits.  This has occurred when performing
	 a GDB "return" command in which the return address is obtained
	 from a 32-bit container on the stack.  */
      assert ((pc & ~0x0fffff) == 0);
    }
  else
    memory[reg_addr (regno)] = val;
  return size;
}
Ejemplo n.º 2
0
int
sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;
  SI val;

  check_desc (sd);

  if (!check_regno (regno))
    return 0;

  size = reg_size (regno);

  if (length != size)
    return 0;

  if (regno == sim_rl78_pc_regnum)
    val = pc;
  else
    val = memory[reg_addr (regno)];

  put_le (buf, length, val);

  return size;
}
void
sim_info (SIM_DESC sd, int verbose)
{
  check_desc (sd);

  printf ("The rx minisim doesn't collect any statistics.\n");
}
void
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p)
{
  check_desc (sd);

  *reason_p = reason;
  *sigrc_p = siggnal;
}
Ejemplo n.º 5
0
int
sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
{
  check_desc (sd);

  mem_put_blk ((int) mem, buf, length);

  return length;
}
Ejemplo n.º 6
0
void
sim_close (SIM_DESC sd, int quitting)
{
  check_desc (sd);

  /* Not much to do.  At least free up our memory.  */
  init_mem ();

  open = 0;
}
Ejemplo n.º 7
0
SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd * abfd, char **argv, char **env)
{
  check_desc (sd);

  if (abfd)
    m32c_load (abfd);

  return SIM_RC_OK;
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{
  check_desc (sd);

  char *p = cmd;

  /* Skip leading whitespace.  */
  while (isspace (*p))
    p++;

  /* Find the extent of the command word.  */
  for (p = cmd; *p; p++)
    if (isspace (*p))
      break;

  /* Null-terminate the command word, and record the start of any
     further arguments.  */
  char *args;
  if (*p)
    {
      *p = '\0';
      args = p + 1;
      while (isspace (*args))
	args++;
    }
  else
    args = p;

  if (strcmp (cmd, "trace") == 0)
    {
      if (strcmp (args, "on") == 0)
	trace = 1;
      else if (strcmp (args, "off") == 0)
	trace = 0;
      else
	printf ("The 'sim trace' command expects 'on' or 'off' "
		"as an argument.\n");
    }
  else if (strcmp (cmd, "verbose") == 0)
    {
      if (strcmp (args, "on") == 0)
	verbose = 1;
      else if (strcmp (args, "noisy") == 0)
	verbose = 2;
      else if (strcmp (args, "off") == 0)
	verbose = 0;
      else
	printf ("The 'sim verbose' command expects 'on', 'noisy', or 'off'"
		" as an argument.\n");
    }
  else
    printf ("The 'sim' command expects either 'trace' or 'verbose'"
	    " as a subcommand.\n");
}
Ejemplo n.º 9
0
SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
		     char * const *argv, char * const *env)
{
  check_desc (sd);

  if (abfd)
    rl78_load (abfd, 0, "sim");

  return SIM_RC_OK;
}
Ejemplo n.º 10
0
int
sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
{
  check_desc (sd);

  if (mem == 0)
    return 0;

  mem_get_blk ((int) mem, buf, length);

  return length;
}
SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
{
  check_desc (sd);

  if (abfd)
    {
      rx_load (abfd);
      build_swap_list (abfd);
    }

  return SIM_RC_OK;
}
Ejemplo n.º 12
0
int
sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
{
  check_desc (sd);

  if (mem >= MEM_SIZE)
    return 0;
  else if (mem + length > MEM_SIZE)
    length = MEM_SIZE - mem;

  mem_put_blk (mem, buf, length);
  return length;
}
Ejemplo n.º 13
0
SIM_RC
sim_load (SIM_DESC sd, char *prog, struct bfd * abfd, int from_tty)
{
  check_desc (sd);

  if (!abfd)
    abfd = open_objfile (prog);
  if (!abfd)
    return SIM_RC_FAIL;

  m32c_load (abfd);

  return SIM_RC_OK;
}
Ejemplo n.º 14
0
SIM_RC
sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty)
{
  check_desc (sd);

  if (!abfd)
    abfd = open_objfile (prog);
  if (!abfd)
    return SIM_RC_FAIL;

  rl78_load (abfd, host_callbacks, "sim");

  return SIM_RC_OK;
}
void
sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
{
  check_desc (sd);

  if (sig_to_deliver != 0)
    {
      fprintf (stderr,
	       "Warning: the rx minisim does not implement "
	       "signal delivery yet.\n" "Resuming with no signal.\n");
    }

  execution_error_clear_last_error ();

  if (step)
    handle_step (decode_opcode ());
  else
    {
      /* We don't clear 'stop' here, because then we would miss
         interrupts that arrived on the way here.  Instead, we clear
         the flag in sim_stop_reason, after GDB has disabled the
         interrupt signal handler.  */
      for (;;)
	{
	  if (stop)
	    {
	      stop = 0;
	      reason = sim_stopped;
	      siggnal = TARGET_SIGNAL_INT;
	      break;
	    }

	  int rc = decode_opcode ();

	  if (execution_error_get_last_error () != SIM_ERR_NONE)
	    {
	      reason = sim_stopped;
	      siggnal = TARGET_SIGNAL_SEGV;
	      break;
	    }

	  if (!RX_STEPPED (rc))
	    {
	      handle_step (rc);
	      break;
	    }
	}
    }
}
Ejemplo n.º 16
0
void
sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
{
  int rc;

  check_desc (sd);

  if (sig_to_deliver != 0)
    {
      fprintf (stderr,
	       "Warning: the rl78 minisim does not implement "
	       "signal delivery yet.\n" "Resuming with no signal.\n");
    }

      /* We don't clear 'stop' here, because then we would miss
         interrupts that arrived on the way here.  Instead, we clear
         the flag in sim_stop_reason, after GDB has disabled the
         interrupt signal handler.  */
  for (;;)
    {
      if (stop)
	{
	  stop = 0;
	  reason = sim_stopped;
	  siggnal = GDB_SIGNAL_INT;
	  break;
	}

      if (hw_breakpoints[pc >> 3]
          && (hw_breakpoints[pc >> 3] & (1 << (pc & 0x7))))
	{
	  reason = sim_stopped;
	  siggnal = GDB_SIGNAL_TRAP;
	  break;
	}
      rc = setjmp (decode_jmp_buf);
      if (rc == 0)
	rc = decode_opcode ();

      if (!RL78_STEPPED (rc) || step)
	{
	  handle_step (rc);
	  break;
	}
    }
}
int
sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
{
  int i;

  check_desc (sd);

  execution_error_clear_last_error ();

  for (i = 0; i < length; i++)
    {
      bfd_vma addr = mem + i;
      int do_swap = addr_in_swap_list (addr);
      mem_put_qi (addr ^ (do_swap ? 3 : 0), buf[i]);

      if (execution_error_get_last_error () != SIM_ERR_NONE)
	return i;
    }

  return length;
}
Ejemplo n.º 18
0
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;
  SI val;

  check_desc (sd);

  if (!check_regno (regno))
    return -1;

  size = reg_size (regno);

  if (length != size)
    return -1;

  val = get_le (buf, length);

  if (regno == sim_rl78_pc_regnum)
    pc = val;
  else
    memory[reg_addr (regno)] = val;
  return size;
}
Ejemplo n.º 19
0
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;

  check_desc (sd);

  if (!check_regno (regno))
    return -1;

  size = reg_size (regno);

  if (length == size)
    {
      DI val = get_le (buf, length);

      switch (regno)
	{
	case m32c_sim_reg_r0_bank0:
	  regs.r[0].r_r0 = val & 0xffff;
	  break;
	case m32c_sim_reg_r1_bank0:
	  regs.r[0].r_r1 = val & 0xffff;
	  break;
	case m32c_sim_reg_r2_bank0:
	  regs.r[0].r_r2 = val & 0xffff;
	  break;
	case m32c_sim_reg_r3_bank0:
	  regs.r[0].r_r3 = val & 0xffff;
	  break;
	case m32c_sim_reg_a0_bank0:
	  regs.r[0].r_a0 = val & addr_mask;
	  break;
	case m32c_sim_reg_a1_bank0:
	  regs.r[0].r_a1 = val & addr_mask;
	  break;
	case m32c_sim_reg_fb_bank0:
	  regs.r[0].r_fb = val & addr_mask;
	  break;
	case m32c_sim_reg_sb_bank0:
	  regs.r[0].r_sb = val & addr_mask;
	  break;
	case m32c_sim_reg_r0_bank1:
	  regs.r[1].r_r0 = val & 0xffff;
	  break;
	case m32c_sim_reg_r1_bank1:
	  regs.r[1].r_r1 = val & 0xffff;
	  break;
	case m32c_sim_reg_r2_bank1:
	  regs.r[1].r_r2 = val & 0xffff;
	  break;
	case m32c_sim_reg_r3_bank1:
	  regs.r[1].r_r3 = val & 0xffff;
	  break;
	case m32c_sim_reg_a0_bank1:
	  regs.r[1].r_a0 = val & addr_mask;
	  break;
	case m32c_sim_reg_a1_bank1:
	  regs.r[1].r_a1 = val & addr_mask;
	  break;
	case m32c_sim_reg_fb_bank1:
	  regs.r[1].r_fb = val & addr_mask;
	  break;
	case m32c_sim_reg_sb_bank1:
	  regs.r[1].r_sb = val & addr_mask;
	  break;

	case m32c_sim_reg_usp:
	  regs.r_usp = val & addr_mask;
	  break;
	case m32c_sim_reg_isp:
	  regs.r_isp = val & addr_mask;
	  break;
	case m32c_sim_reg_pc:
	  regs.r_pc = val & membus_mask;
	  break;
	case m32c_sim_reg_intb:
	  regs.r_intbl = (val & membus_mask) & 0xffff;
	  regs.r_intbh = (val & membus_mask) >> 16;
	  break;
	case m32c_sim_reg_flg:
	  regs.r_flags = val & 0xffff;
	  break;

	  /* These registers aren't implemented by the minisim.  */
	case m32c_sim_reg_svf:
	case m32c_sim_reg_svp:
	case m32c_sim_reg_vct:
	case m32c_sim_reg_dmd0:
	case m32c_sim_reg_dmd1:
	case m32c_sim_reg_dct0:
	case m32c_sim_reg_dct1:
	case m32c_sim_reg_drc0:
	case m32c_sim_reg_drc1:
	case m32c_sim_reg_dma0:
	case m32c_sim_reg_dma1:
	case m32c_sim_reg_dsa0:
	case m32c_sim_reg_dsa1:
	case m32c_sim_reg_dra0:
	case m32c_sim_reg_dra1:
	  return 0;

	default:
	  fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
		   regno);
	  return 0;
	}
    }
Ejemplo n.º 20
0
int
sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;

  check_desc (sd);

  if (!check_regno (regno))
    return 0;

  size = reg_size (regno);
  if (length == size)
    {
      DI val;

      switch (regno)
	{
	case m32c_sim_reg_r0_bank0:
	  val = regs.r[0].r_r0;
	  break;
	case m32c_sim_reg_r1_bank0:
	  val = regs.r[0].r_r1;
	  break;
	case m32c_sim_reg_r2_bank0:
	  val = regs.r[0].r_r2;
	  break;
	case m32c_sim_reg_r3_bank0:
	  val = regs.r[0].r_r3;
	  break;
	case m32c_sim_reg_a0_bank0:
	  val = regs.r[0].r_a0;
	  break;
	case m32c_sim_reg_a1_bank0:
	  val = regs.r[0].r_a1;
	  break;
	case m32c_sim_reg_fb_bank0:
	  val = regs.r[0].r_fb;
	  break;
	case m32c_sim_reg_sb_bank0:
	  val = regs.r[0].r_sb;
	  break;
	case m32c_sim_reg_r0_bank1:
	  val = regs.r[1].r_r0;
	  break;
	case m32c_sim_reg_r1_bank1:
	  val = regs.r[1].r_r1;
	  break;
	case m32c_sim_reg_r2_bank1:
	  val = regs.r[1].r_r2;
	  break;
	case m32c_sim_reg_r3_bank1:
	  val = regs.r[1].r_r3;
	  break;
	case m32c_sim_reg_a0_bank1:
	  val = regs.r[1].r_a0;
	  break;
	case m32c_sim_reg_a1_bank1:
	  val = regs.r[1].r_a1;
	  break;
	case m32c_sim_reg_fb_bank1:
	  val = regs.r[1].r_fb;
	  break;
	case m32c_sim_reg_sb_bank1:
	  val = regs.r[1].r_sb;
	  break;

	case m32c_sim_reg_usp:
	  val = regs.r_usp;
	  break;
	case m32c_sim_reg_isp:
	  val = regs.r_isp;
	  break;
	case m32c_sim_reg_pc:
	  val = regs.r_pc;
	  break;
	case m32c_sim_reg_intb:
	  val = regs.r_intbl * 65536 + regs.r_intbl;
	  break;
	case m32c_sim_reg_flg:
	  val = regs.r_flags;
	  break;

	  /* These registers aren't implemented by the minisim.  */
	case m32c_sim_reg_svf:
	case m32c_sim_reg_svp:
	case m32c_sim_reg_vct:
	case m32c_sim_reg_dmd0:
	case m32c_sim_reg_dmd1:
	case m32c_sim_reg_dct0:
	case m32c_sim_reg_dct1:
	case m32c_sim_reg_drc0:
	case m32c_sim_reg_drc1:
	case m32c_sim_reg_dma0:
	case m32c_sim_reg_dma1:
	case m32c_sim_reg_dsa0:
	case m32c_sim_reg_dsa1:
	case m32c_sim_reg_dra0:
	case m32c_sim_reg_dra1:
	  return 0;

	default:
	  fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
		   regno);
	  return -1;
	}

      put_le (buf, length, val);
    }

  return size;
}
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;
  DI val;

  check_desc (sd);

  if (!check_regno (regno))
    return 0;

  size = reg_size (regno);

  if (length != size)
    return 0;

  if (rx_big_endian)
    val = get_be (buf, length);
  else
    val = get_le (buf, length);

  switch (regno)
    {
    case sim_rx_r0_regnum:
      put_reg (0, val);
      break;
    case sim_rx_r1_regnum:
      put_reg (1, val);
      break;
    case sim_rx_r2_regnum:
      put_reg (2, val);
      break;
    case sim_rx_r3_regnum:
      put_reg (3, val);
      break;
    case sim_rx_r4_regnum:
      put_reg (4, val);
      break;
    case sim_rx_r5_regnum:
      put_reg (5, val);
      break;
    case sim_rx_r6_regnum:
      put_reg (6, val);
      break;
    case sim_rx_r7_regnum:
      put_reg (7, val);
      break;
    case sim_rx_r8_regnum:
      put_reg (8, val);
      break;
    case sim_rx_r9_regnum:
      put_reg (9, val);
      break;
    case sim_rx_r10_regnum:
      put_reg (10, val);
      break;
    case sim_rx_r11_regnum:
      put_reg (11, val);
      break;
    case sim_rx_r12_regnum:
      put_reg (12, val);
      break;
    case sim_rx_r13_regnum:
      put_reg (13, val);
      break;
    case sim_rx_r14_regnum:
      put_reg (14, val);
      break;
    case sim_rx_r15_regnum:
      put_reg (15, val);
      break;
    case sim_rx_isp_regnum:
      put_reg (isp, val);
      break;
    case sim_rx_usp_regnum:
      put_reg (usp, val);
      break;
    case sim_rx_intb_regnum:
      put_reg (intb, val);
      break;
    case sim_rx_pc_regnum:
      put_reg (pc, val);
      break;
    case sim_rx_ps_regnum:
      put_reg (psw, val);
      break;
    case sim_rx_bpc_regnum:
      put_reg (bpc, val);
      break;
    case sim_rx_bpsw_regnum:
      put_reg (bpsw, val);
      break;
    case sim_rx_fintv_regnum:
      put_reg (fintv, val);
      break;
    case sim_rx_fpsw_regnum:
      put_reg (fpsw, val);
      break;
    default:
      fprintf (stderr, "rx minisim: unrecognized register number: %d\n",
	       regno);
      return -1;
    }

  return size;
}
int
sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
  size_t size;
  DI val;

  check_desc (sd);

  if (!check_regno (regno))
    return 0;

  size = reg_size (regno);

  if (length != size)
    return 0;

  switch (regno)
    {
    case sim_rx_r0_regnum:
      val = get_reg (0);
      break;
    case sim_rx_r1_regnum:
      val = get_reg (1);
      break;
    case sim_rx_r2_regnum:
      val = get_reg (2);
      break;
    case sim_rx_r3_regnum:
      val = get_reg (3);
      break;
    case sim_rx_r4_regnum:
      val = get_reg (4);
      break;
    case sim_rx_r5_regnum:
      val = get_reg (5);
      break;
    case sim_rx_r6_regnum:
      val = get_reg (6);
      break;
    case sim_rx_r7_regnum:
      val = get_reg (7);
      break;
    case sim_rx_r8_regnum:
      val = get_reg (8);
      break;
    case sim_rx_r9_regnum:
      val = get_reg (9);
      break;
    case sim_rx_r10_regnum:
      val = get_reg (10);
      break;
    case sim_rx_r11_regnum:
      val = get_reg (11);
      break;
    case sim_rx_r12_regnum:
      val = get_reg (12);
      break;
    case sim_rx_r13_regnum:
      val = get_reg (13);
      break;
    case sim_rx_r14_regnum:
      val = get_reg (14);
      break;
    case sim_rx_r15_regnum:
      val = get_reg (15);
      break;
    case sim_rx_isp_regnum:
      val = get_reg (isp);
      break;
    case sim_rx_usp_regnum:
      val = get_reg (usp);
      break;
    case sim_rx_intb_regnum:
      val = get_reg (intb);
      break;
    case sim_rx_pc_regnum:
      val = get_reg (pc);
      break;
    case sim_rx_ps_regnum:
      val = get_reg (psw);
      break;
    case sim_rx_bpc_regnum:
      val = get_reg (bpc);
      break;
    case sim_rx_bpsw_regnum:
      val = get_reg (bpsw);
      break;
    case sim_rx_fintv_regnum:
      val = get_reg (fintv);
      break;
    case sim_rx_fpsw_regnum:
      val = get_reg (fpsw);
      break;
    case sim_rx_acc_regnum:
      val = ((DI) get_reg (acchi) << 32) | get_reg (acclo);
      break;
    default:
      fprintf (stderr, "rx minisim: unrecognized register number: %d\n",
	       regno);
      return -1;
    }

  if (rx_big_endian)
    put_be (buf, length, val);
  else
    put_le (buf, length, val);

  return size;
}