static int footswitch_disable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & ENABLE_BIT) == 0)
return 0;
rc = setup_clocks(fs);
if (rc)
return rc;
clk_set_flags(fs->core_clk, CLKFLAG_NORETAIN);
if (fs->bus_port0) {
rc = msm_bus_axi_porthalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 halt failed.\n", fs->desc.name);
goto err;
}
}
if (fs->bus_port1) {
rc = msm_bus_axi_porthalt(fs->bus_port1);
if (rc) {
pr_err("%s port 1 halt failed.\n", fs->desc.name);
goto err_port2_halt;
}
}
for (clock = fs->clk_data; clock->clk; clock++)
;
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
udelay(RESET_DELAY_US);
restore_clocks(fs);
regval |= CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
regval &= ~ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
fs->is_enabled = false;
return 0;
err_port2_halt:
msm_bus_axi_portunhalt(fs->bus_port0);
err:
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN);
restore_clocks(fs);
return rc;
}
static int footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = true;
mutex_unlock(&claim_lock);
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & (ENABLE_BIT | CLAMP_BIT)) == ENABLE_BIT)
return 0;
rc = setup_clocks(fs);
if (rc)
return rc;
if (fs->bus_port0) {
rc = msm_bus_axi_portunhalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 unhalt failed.\n", fs->desc.name);
goto err;
}
}
if (fs->bus_port1) {
rc = msm_bus_axi_portunhalt(fs->bus_port1);
if (rc) {
pr_err("%s port 1 unhalt failed.\n", fs->desc.name);
goto err_port2_halt;
}
}
for (clock = fs->clk_data; clock->clk; clock++)
;
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
udelay(RESET_DELAY_US);
regval |= ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
mb();
udelay(1);
regval &= ~CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
for (clock = fs->clk_data; clock->clk; clock++)
clk_reset(clock->clk, CLK_RESET_DEASSERT);
if (fs->desc.id == FS_GFX3D) {
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
udelay(RESET_DELAY_US);
clk_reset(fs->core_clk, CLK_RESET_DEASSERT);
udelay(RESET_DELAY_US);
}
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN);
restore_clocks(fs);
fs->is_enabled = true;
return 0;
err_port2_halt:
msm_bus_axi_porthalt(fs->bus_port0);
err:
restore_clocks(fs);
return rc;
}
static int msm_ssphy_qmp_reset(struct usb_phy *uphy)
{
struct msm_ssphy_qmp *phy = container_of(uphy, struct msm_ssphy_qmp,
phy);
int ret;
dev_dbg(uphy->dev, "Resetting QMP phy\n");
if (!phy->clk_enabled) {
ret = msm_ssphy_qmp_init_clocks(phy);
if (ret) {
dev_err(uphy->dev, "failed to init clocks %d\n", ret);
return ret;
}
}
/* Assert USB3 PHY reset */
if (phy->phy_com_reset) {
ret = clk_reset(phy->phy_com_reset, CLK_RESET_ASSERT);
if (ret) {
dev_err(uphy->dev, "phy_com_reset clk assert failed\n");
return ret;
}
}
/* Assert USB3 PHY reset */
if (phy->phy_phy_reset) {
ret = clk_reset(phy->phy_phy_reset, CLK_RESET_ASSERT);
if (ret) {
dev_err(uphy->dev, "phy_phy reset assert failed\n");
goto deassert_phy_com_reset;
}
} else {
ret = clk_reset(phy->pipe_clk, CLK_RESET_ASSERT);
if (ret) {
dev_err(uphy->dev, "pipe_clk reset assert failed\n");
goto deassert_phy_com_reset;
}
}
/* Assert USB3 PHY CSR reset */
ret = clk_reset(phy->phy_reset, CLK_RESET_ASSERT);
if (ret) {
dev_err(uphy->dev, "phy_reset clk assert failed\n");
goto deassert_phy_phy_reset;
}
/* Deassert USB3 PHY CSR reset */
ret = clk_reset(phy->phy_reset, CLK_RESET_DEASSERT);
if (ret) {
dev_err(uphy->dev, "phy_reset clk deassert failed\n");
goto deassert_phy_phy_reset;
}
/* Deassert USB3 PHY reset */
if (phy->phy_phy_reset) {
ret = clk_reset(phy->phy_phy_reset, CLK_RESET_DEASSERT);
if (ret) {
dev_err(uphy->dev, "phy_phy reset deassert failed\n");
goto deassert_phy_com_reset;
}
} else {
ret = clk_reset(phy->pipe_clk, CLK_RESET_DEASSERT);
if (ret) {
dev_err(uphy->dev, "pipe_clk reset deassert failed\n");
goto deassert_phy_com_reset;
}
}
if (phy->phy_com_reset) {
ret = clk_reset(phy->phy_com_reset, CLK_RESET_DEASSERT);
if (ret) {
dev_err(uphy->dev, "phy_com_reset clk deassert failed\n");
return ret;
}
}
return 0;
deassert_phy_phy_reset:
if (phy->phy_phy_reset)
clk_reset(phy->phy_phy_reset, CLK_RESET_DEASSERT);
else
clk_reset(phy->pipe_clk, CLK_RESET_DEASSERT);
deassert_phy_com_reset:
if (phy->phy_com_reset)
clk_reset(phy->phy_com_reset, CLK_RESET_DEASSERT);
phy->in_suspend = false;
return ret;
}
static int msm_dai_q6_auxpcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct msm_dai_q6_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc = 0;
struct msm_dai_auxpcm_pdata *auxpcm_pdata =
(struct msm_dai_auxpcm_pdata *) dai->dev->platform_data;
mutex_lock(&aux_pcm_mutex);
if (aux_pcm_count == 2) {
dev_dbg(dai->dev, "%s(): dai->id %d aux_pcm_count is 2. Just"
" return.\n", __func__, dai->id);
mutex_unlock(&aux_pcm_mutex);
return 0;
} else if (aux_pcm_count > 2) {
dev_err(dai->dev, "%s(): ERROR: dai->id %d"
" aux_pcm_count = %d > 2\n",
__func__, dai->id, aux_pcm_count);
mutex_unlock(&aux_pcm_mutex);
return 0;
}
aux_pcm_count++;
if (aux_pcm_count == 2) {
dev_dbg(dai->dev, "%s(): dai->id %d aux_pcm_count = %d after "
" increment\n", __func__, dai->id, aux_pcm_count);
mutex_unlock(&aux_pcm_mutex);
return 0;
}
pr_debug("%s:dai->id:%d aux_pcm_count = %d. opening afe\n",
__func__, dai->id, aux_pcm_count);
rc = afe_q6_interface_prepare();
if (IS_ERR_VALUE(rc))
dev_err(dai->dev, "fail to open AFE APR\n");
/*
* For AUX PCM Interface the below sequence of clk
* settings and afe_open is a strict requirement.
*
* Also using afe_open instead of afe_port_start_nowait
* to make sure the port is open before deasserting the
* clock line. This is required because pcm register is
* not written before clock deassert. Hence the hw does
* not get updated with new setting if the below clock
* assert/deasset and afe_open sequence is not followed.
*/
clk_reset(pcm_clk, CLK_RESET_ASSERT);
afe_open(PCM_RX, &dai_data->port_config, dai_data->rate);
afe_open(PCM_TX, &dai_data->port_config, dai_data->rate);
rc = clk_set_rate(pcm_clk, auxpcm_pdata->pcm_clk_rate);
if (rc < 0) {
pr_err("%s: clk_set_rate failed\n", __func__);
return rc;
}
clk_enable(pcm_clk);
//HTC_AUD++
//There is downlink no sound when receiving a MT-call.
//Adding a delay to solve this issue.
usleep(15000);
//HTC_AUD--
clk_reset(pcm_clk, CLK_RESET_DEASSERT);
mutex_unlock(&aux_pcm_mutex);
return rc;
}
int msm_cam_core_reset(void)
{
struct clk *clk1;
int rc = 0;
clk1 = clk_get(NULL, "csi_vfe_clk");
if (IS_ERR(clk1)) {
pr_err("%s: did not get csi_vfe_clk\n", __func__);
return PTR_ERR(clk1);
}
rc = clk_reset(clk1, CLK_RESET_ASSERT);
if (rc) {
pr_err("%s:csi_vfe_clk assert failed\n", __func__);
clk_put(clk1);
return rc;
}
usleep_range(1000, 1200);
rc = clk_reset(clk1, CLK_RESET_DEASSERT);
if (rc) {
pr_err("%s:csi_vfe_clk deassert failed\n", __func__);
clk_put(clk1);
return rc;
}
clk_put(clk1);
clk1 = clk_get(NULL, "csi_clk");
if (IS_ERR(clk1)) {
pr_err("%s: did not get csi_clk\n", __func__);
return PTR_ERR(clk1);
}
rc = clk_reset(clk1, CLK_RESET_ASSERT);
if (rc) {
pr_err("%s:csi_clk assert failed\n", __func__);
clk_put(clk1);
return rc;
}
usleep_range(1000, 1200);
rc = clk_reset(clk1, CLK_RESET_DEASSERT);
if (rc) {
pr_err("%s:csi_clk deassert failed\n", __func__);
clk_put(clk1);
return rc;
}
clk_put(clk1);
clk1 = clk_get(NULL, "csi_pclk");
if (IS_ERR(clk1)) {
pr_err("%s: did not get csi_pclk\n", __func__);
return PTR_ERR(clk1);
}
rc = clk_reset(clk1, CLK_RESET_ASSERT);
if (rc) {
pr_err("%s:csi_pclk assert failed\n", __func__);
clk_put(clk1);
return rc;
}
usleep_range(1000, 1200);
rc = clk_reset(clk1, CLK_RESET_DEASSERT);
if (rc) {
pr_err("%s:csi_pclk deassert failed\n", __func__);
clk_put(clk1);
return rc;
}
clk_put(clk1);
return rc;
}
static int gfx2d_footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = 1;
mutex_unlock(&claim_lock);
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
goto out;
/* Un-halt all bus ports in the power domain. */
if (fs->bus_port1) {
rc = msm_bus_axi_portunhalt(fs->bus_port1);
if (rc) {
pr_err("%s: Port 1 unhalt failed.\n", __func__);
goto out;
}
}
/* Disable core clock. */
clk_disable(fs->core_clk);
/* (Re-)Assert resets for all clocks in the clock domain, since
* footswitch_enable() is first called before footswitch_disable()
* and resets should be asserted before power is restored. */
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_ASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_ASSERT);
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(20);
/* Enable the power rail at the footswitch. */
regval = readl(fs->gfs_ctl_reg);
regval |= ENABLE_BIT;
writel(regval, fs->gfs_ctl_reg);
udelay(1);
/* Un-clamp the I/O ports. */
regval &= ~CLAMP_BIT;
writel(regval, fs->gfs_ctl_reg);
/* Deassert resets for all clocks in the power domain. */
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_DEASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_DEASSERT);
clk_reset(fs->core_clk, CLK_RESET_DEASSERT);
udelay(20);
/* Re-enable core clock. */
clk_enable(fs->core_clk);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = 1;
out:
return rc;
}
